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基于FPGA的规则(3,6)LDPC码译码器
Authors
李智明
王琳
肖旻
范雷
Publication date
25 December 2004
Publisher
Abstract
基于软判决译码规则,采用完全并行的解码结构,使用Verilog硬件描述语言,在Xilinx公司的FPGA(Virtex-2 xcv 1000)上实现了码率为1/2、帧长为20bit的规则(3,)LDPC码的译码器,最大传输速率可达20Mbps。对LDPC码的实际应用具有重要的推动作用
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Last time updated on 10/06/2020