Issued as final reportGoodrich Corporatio

Ayazi, Farrokh

Casinovi, Giorgio

Scholarly Materials And Research @ Georgia Tech

THROUGH-SILICON-VIA PROCESS DEVELOPMENTGoodrich CorporationFinal Report, June 2010CONTENTSo TSVo Poly layer patternedo Trench top completely sealedo Verified by etching back shown in SEM’s o A wafer cleaved for profileo A small void exit only at the bottom of the trenches shown in SEM’so Resistivity measured from 4-point probeo 0.008 Ω-cmo Parasitic capacitance measuredo ~16 pF with LCR meter2VIA CLUSTERS SEEN FROM THE SURFACE315 um wide opening Vias23 um wide opening ViasThe two SEM’s above show the patterned poly layers with clusters of vias isolated by rectangular sections.TOP VIEW OF THE VIAS AT THE OPENING415 um wide opening Vias23 um wide opening ViasBoth vias are completely filled and sealed from the top as shown in the above SEM’s.  The different concentric pattern at the openings are due to the two-time etching back and three-time poly refill.  This was further verified by etching back from the poly from the top for 10 um.TOP VIEW OF THE VIA OPENING AFTER 10-UM ETCH BACK USING BOSCH PROCESS515 um wide opening Vias23 um wide opening ViasIt might appear bottomless but in fact sealed.  The layers represent the number of etching cycles.TSV CROSS-SECTION615 um wide opening Vias23 um wide opening ViasAs seen in the x-section.  There are still a smaller void present in the trenches.  The diameter of the voids is about 2.5 um.  The length of the large vias is about 80 um more than the small ones.  The trenches seem to have a very straight profiles poly voids seem to present at the bottom quarter of the vias.PARASITIC CAPACITANCE APPROXIMATIONo Calculation based on parallel plate model7dAC ε= , where A is the area of the plates; d is the thickness of oxidee l; and ε is the dielectric constant of oxide.pFumumumumFC 371.14600.138423/10854.89.324 18 ≈××××××≈ − πThe measured value using Agilent E4980A Precision LCR meter is approximately 16.0 pF, under the conditions of 20 Hz and voltage level of 2V.NEXT UPWafers are ready to be sent to be thinned and polished from the backside down to 295 +/-5 um if the silicon dioxide layer does not require any patterning.8

Through-silicon-via process development

https://smartech.gatech.edu/bitstream/1853/61008/1/113161_Goodrich_Final_Report.pdf

Through-silicon-via process development

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