This work is the result of the definition, design and evaluation of a novel method to interconnect
the computational elements - commonly known as Configurable Analogue Blocks (CABs) - of
a programmable analogue array. This method is proposed for total or partial replacement of the
conventional methods due to serious limitations of the latter in terms of scalability.
With this method, named Asynchronous Spike Event Coding (ASEC) scheme, analogue signals
from CABs outputs are encoded as time instants (spike events) dependent upon those signals
activity and are transmitted asynchronously by employing the Address Event Representation
(AER) protocol. Power dissipation is dependent upon input signal activity and no spike events
are generated when the input signal is constant.
On-line, programmable computation is intrinsic to ASEC scheme and is performed without additional
hardware. The ability of the communication scheme to perform computation enhances
the computation power of the programmable analogue array. The design methodology and a
CMOS implementation of the scheme are presented together with test results from prototype
integrated circuits (ICs)