학위논문 (석사)-- 서울대학교 대학원 공과대학 컴퓨터공학부, 2017. 8. 이창건.Mixed-criticality systems integrate tasks with various levels of criticality onto a same hardware platform. Critical tasks require tight bounding of worst-case latency at any cost, yet for non-critical tasks it is important to provide high performance as much as possible. From this, a tough design concern ariseshow to achieve the conflicting demands of performance isolation for critical tasks and efficient sharing for non-critical tasks in terms of shared DRAM bandwidth and capacity?
Recently, modern mixed-criticality systems are facing rapid change in workloads. One of the biggest challenges among this is the advent of memory-intensive workloads in line with migration to multicore. Memory intensive workloads significantly exacerbate contention and interference problems in shared memory resources of multicore architectures. This not only endangers tight bounding of worst-case latency of critical tasks, but also, if not properly addressed, can lead to significant performance penalty and unfairness among non-critical tasks.
In this paper, we take workload-driven approach and propose a novel workload-aware memory controller design for mixed-criticality system that can successfully achieve both of the conflicting demands in the presence of memory-intensive workloads. Based on the key observation that memory access pattern of an application captures major memory requirements of the application, our memory controller manages shared DRAM as a set of memory access pattern-aware partitions - latency sensitive, locality sensitive, and bandwidth sensitive. Our design allocates bandwidth and capacity customized to each partitions needs. By using bank partitioning and request batching with prioritizing, we guarantee short worst-case latency for critical tasks and high performance and fairness to non-critical tasks.I. Introduction 1
II. Background on DRAM Basics 4
2.1 DRAM Architecture and Characteristics 4
2.2 DRAM Memory Controller 6
2.3 Bank Partitioning 8
2.4 Memory Access Patterns 8
III. Observation 10
IV. Memory Access Pattern-Centric Memory Controller Design 16
4.1 Memory Controller Architecture 16
4.1.1 Memory access pattern-aware bank partitioning 17
4.1.2 Partition-based prioritization and request batching 17
4.2 Worst-Case Interference Delay Analysis 18
V. Evaluation 21
5.1 Experiment Setup 21
5.2 Performance result of non-critical tasks 22
VI. Related Work 24
VII. Conclusion 26
References 27Maste
