In this paper a novel pipelining approach applicable to Winograd Fourier transforms is presented. The novel approach makes use of reconfigurable multiplier blocks to implement the real multipliers required for the transform as well as sharing the hardware resources among additions. The additions are realized using modified forms of butterfly circuits. The novel approach is tested on a 5-point Winograd Fourier transform and the circuit area and power dissipation of the design are estimated using an in-house power estimation tool and compared to the state-of-the- art approaches

Angeletti, P.

Brown, S.

Coskun, A.

Hughes, R.

Kale, I.

Morling, R.C.S.

WestminsterResearch

WestminsterResearchhttp://www.westminster.ac.uk/westminsterresearch The Design of Low Complexity Low Power Pipelined Short Length Winograd Fourier TransformsCoskun, A., Kale, I., Morling, R.C.S., Hughes, R., Brown, S. and Angeletti, P. This is a copy of the author’s accepted version of a paper subsequently published in the proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1 to 5 June 2014.It is available online at:https://dx.doi.org/10.1109/ISCAS.2014.6865556© 2014 IEEE . Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.ukThe Design of Low Complexity Low PowerPipelined Short Length Winograd FourierTransformsAdem Coskun, Izzet Kale, Richard C. S. MorlingApplied DSP and VLSI Research GroupUniversity of WestminsterLondon, W1W 6UW, United Kingdomadem@alptron.com, kalei@westminster.ac.ukRobert Hughes, Stephen BrownEADS Astrium LtdStevenage, SG1 2AS, United Kingdomrobert.hughes@astrium.eads.net,stephen.brown@astrium.eads.netPiero AngelettiEuropean Space Agencypiero.angeletti@esa.intAbstract—In this paper a novel pipelining approach applicableto Winograd Fourier transforms is presented. The novel approachmakes use of reconfigurable multiplier blocks to implement thereal multipliers required for the transform as well as sharing thehardware resources among additions. The additions are realizedusing modified forms of butterfly circuits. The novel approach istested on a 5-point Winograd Fourier transform and the circuitarea and power dissipation of the design are estimated using anin-house power estimation tool and compared to the state-of-the-art approaches.I. INTRODUCTIONWinograd Fourier Transform (WFT) [1] algorithm is highlypreferable in designs that involves Discrete Fourier Transform(DFT). Twiddle factor multiplication is not required for WFT,which in turn reduces the number of real multipliers needed.Because multipliers are more resource demanding than othercircuit components, WFT is regarded as a power efficienttransform covering a smaller circuit area. Especially WFTswith blocklengths of 2, 3, 5, 7, 8, 9 and 16 are widely usedin Digital Signal Processing (DSP) applications, the details ofwhich can be found in [7],[6].It is possible to pipeline several short length WFTs togenerate transforms of larger sizes [2], [3]. However, realizinga pipelined structure for short length WFTs is difficult dueto the irregularity in the flow of the signal within thesetransforms. In the next section we will give more details onWFT and present our novel approach on a 5-point WFT.II. WINOGRAD FOURIER TRANSFORM ALGORITHMThe WFT [1] algorithm allows the DFT matrixW =26666641 1 1 1    11 ! !2 !3    !N 11 !2 !4 !6    !2(N 1)..................1 !(N 1) !2(N 1) !3(N 1)    !(N 1)23777775(1)of size NN to be decomposed into three matrices as followsW = S1MS2; (2)where ! = e j2N , S1 and S2 are of size NM and MNand composed of only  1; 0 and 1. M is a MM diagonalmatrix being composed of either purely real or purely imag-inary numbers. For N = 5, which is taken as the referencedesign for this paper,S1=2666641 0 0 0 0 01  1  1 0  1 11  1 1  1 1 01  1 1 1  1 01  1  1 0 1  1377775;S2=266666641 1 1 1 10 1 1 1 10 1  1  1 10 1 0 0  10 1 1  1  10 0 1  1 037777775(3)andM = diag[ m0; m1; m2; m3; m4; m5 ]= diag[ 1; 1  cos(u) + cos(2u)2;cos(2u)  cos(u)2;j(sin(u) + sin(2u)); j(sin(u)); j(sin(u)  sin(2u))];(4)where diag[m0; :::;mM ] represents a diagonal matrix, mi,for i = 0; ::;M , being its diagonal components and u =2=5. Matrix W is used to obtain X = Wx, where x =[x0; x1; x2; x4; x3]T is the data samples. Please note herethat both x and X are not in their natural order, which caneasily be arranged by designing the address generators to pickthe right locations at the input and the output buffer for the5-point WFT.The top plot in Fig.1 shows the signal flow graph for 5-point WFT given in (3) and (4). Stages 1 to 3, Stage 4 andStage 5 to 7 are to implement operations required by S2,M and S1 respectively. Here the components of vector x isapplied to the system all in parallel. However, this is just therepresentation and in fact the samples are assumed to arrivesequentially. The black triangles (I) indicate multiplicationsby constants. The black dots () are the additions. As can beseen for 5-point WFT 17 complex additions and 5 real-by-complex multiplications are needed if the data samples vector -1-1-1 -1-1-1-1-1-1B1 B2Stage2Stage1 Stage3 Stage4 Stage5 Stage6 Stage7B3 B4 B5 B6 B7x0x1x2x4x3X0X2X4X3X1m0m1m4m2m3Fig. 1. The plot on the top is the signal flow graph for 5-point WFT and theplot on the bottom is the representation of our pipelined design with sevenstages.x is complex. Pay attention to the irregularity in this graph,which avoids a pipelined design to be deployed straightaway.In [5] the structure of the 5-point WFT has been modified inorder to set the symmetry in its signal flow graph. However,this modification brought the need for complex-by-complexmultiplications in the multiplier stage (i.e. Stage 4 in Fig.1),which of course increases the complexity of the structure.In our design given in the following section the pipeliningis introduced to the WFT without modifying its signal flowgraph.III. PIPELINED 5-POINT WFTOur design is a 7-stage pipelined architecture(B1; B2; : : : ; B7), which is depicted in the plot at thebottom of in Fig.1. What stage of the pipelined architecturecorresponds to which part of the 5-point WFT signal flowgraph is clearly shown in Fig.1 with vertical dashed lines.It is pipelined and the components of x are fed sequentiallyinto the pipelined circuit in the same order that x is formed.There are two types of components comprising the structureof the novel design. The Reconfigurable Multiplier Block(ReMB) [8] and modified butterfly circuits.Designing the ReMB: In Fig.1, B4 is the stage wherethe multiplications take place. Therefore, it corresponds tothe operations required by the diagonal matrix M. As thedata samples fed into the pipelined structure sequentially, B4should be capable of performing one distinct multiplicationat a time instance. This can be achieved using a ReMB [9],[10]. Here we assume each data sample is quantized using11 bits (2 being integer and 9 for fractional bits). From their NegReMBSwitchControlLogic (a) >>1>>1>>1>>2>>2>>2>>3>>6>>3>>4>>1++0>>3+i2i1OUTIN(b)Fig. 2. (a) The structure of the circuit that implements operations required byM (b) The ReMB which implements the multiplication with the coefficientsm1; :::;m5.Canonical Signed Digit (CSD) representations, each multipli-cation coefficient, i.e. m1; :::;m5, can be implemented usingthe ReMB given in Fig.2(b). Fig.2(b) is composed of 3 addersand 3 multiplexers, each having 5 inputs. The order of theinputs to each multiplexer is set in accordance with the orderof the multiplication coefficients used for the 5-point WFT.For example; if m1 is to be implemented, the first inputs forall three multiplexers should be activated. Carry-in inputs i1and i2 are selected based on if the adder is to be implementedas a subtractor or not. As can be seen, some inputs to themultiplexers are inverted right before multiplexing. This alsoserves the need for the use of a subtractor in generatingmultiplications. The symbol >> represents hard-wired shiftoperation with the value following this sign showing howmany shifts are needed. Each shift operation in Fig.2(b)belongs to the branch that goes right below them.Due to multiplication with complex signals, two ReMBs areneeded, one for the real and the second for the imaginary partof the incoming complex signal. Fig.2(a) shows two ReMBs,the internal architectures of which are given in Fig.2(b). The IN∑∑+-OUT++c2c1c2c1 c2c2 c3 c4c1c3c1c1c5L1L2c4 Fig. 3. Butterfly circuit that implements the additions required by matrix S1rest of Fig.2(a) is the negator and a 2x2 switch, which areneeded due to the multiplication with j as required in (4), form3;m4 and m5. For the other two multiplication coefficientsthese two components are deactivated by the control logic,which also provides the control signals and carry-in valuesfor each one of the ReMBs.Modified butterfly circuit: The first three stages in Fig.1implements the operations needed by S2, where there are 3full and 2 half butterfly circuits (i.e. 5 butterfly operations). Itis in fact possible to accommodate only one butterfly circuitand perform all of the 5 operations making use of this singlebutterfly circuit, which will save a lot of hardware as this willget rid of most of the adders and subtractors needed. Because itis a 5 point Fourier transform, all of the 5 butterfly operationswill be accomplished within the duration of the transformwithout causing any delays. Fig.3 shows the modified butterflycircuit, being composed of an adder and a subtractor, alongwith several multiplexers and registers to operate the processedsignals inside the processing element. The square-shaped com-ponents are registers and where concatenated they representshift-registers. These registers are assumed to be enabled atevery clock signal. On the other hand the latches L1 and L2are enabled on when control signals c5 and c6 are active.To operate the whole system synchronously, a 3-bit counteris required that counts from 001 to 101 bit-wise. The controlsignals needed to operate the system in Fig.3 are given in TableI. In total of 6 signals are needed and Table I shows which ofthese control signals are active at which counter instance.The solution for the modification of a butterfly circuit issummarized in Fig.4. The modified butterfly circuit has twoTABLE ICONTROL SIGNALS IN THE PIPELINED 5-POINT WFT CIRCUITCounter Value Control Signals that are active001 c2; c3010 c1; c3; c4011 c2; c3; c5100 c4101 c4 ButterflyCircuitShift RegistersStageRegistersOUTINControl Logic Fig. 4. The structure of the modified butterfly circuit that is designed tomerge several stages within a WFT. Three of these circuits are needed torealize a 5-point WFT.sets of registers, one that coordinates the butterfly operations(shown as shift registers in Fig.4) and the other guides thesamples from one stage to the next stage in the signal flowgraph (named shift registers in Fig.4). The maximum numberof stage registers is equal to the number of stages that arecombined under one modified butterfly circuit. Due to the ir-regularity of the WFT, extra multiplexers and registers/latchesare required in addition to the components depicted in Fig.4.The timing is under the control of the control logic same asFig.2(a).One butterfly circuit is enough to implement stages B5 andB6, which is in similar structure shown in Fig.4. Note thatthese two stages need for 4 butterfly operations (1 full and3 half butterfly operations), which justifies the use of onlyone butterfly circuit to realize B5 and B6. We leave it to thereader to derive the lay-out of this modified butterfly circuit. Aconventional butterfly circuit without any modifications wouldbe enough to implement the last stage.IV. COMPARATIVE STUDYIn order to understand the possible savings with the useof our novel approach, in terms of both power dissipation andcircuit area, we have implemented several approaches from theliterature to realize a 5-point WFT by using an in-house costestimation tool and created the content for Table II. Powerdissipation for the designed circuits are estimated in mWand the circuits area is in terms of gates. Power dissipationTABLE IICOMPARISON OF APPROACHES FOR IMPLEMENTING 5-POINT WFTApproach Power Dissipation (mW) Circuit Area (gates)WFT 5.69 35.46kKolbaWFT 5.45 33.87kMlessWFT 4.58 20.74kRegWFT 7.71 18.90kPipelinedWFT 3.67 7.70khas been evaluated considering the activation rate of eachprocessing component in the circuit individually.In Table II, WFT is the straightforward implementation ofthe 5-point Winograd Fourier transform. This structure is stillin use [11],[12] and needs for 5 multipliers. Kolba and Park’sdesign [3] (which we name KolbaWFT) on the other handneeds for only 4 multipliers and a shift operation. Therefore, itis less complex. Rather than using general purpose multipliers,a multiplierless approach may also be accommodated, as sug-gested in [13], because of the fact that the coefficients for themultiplication is fixed. This approach appears as MlessWFTAin Table II. The savings if a multiplierless approach is obviousover the conventional approaches.Pipelining the 5-point WFT using the approach in [5](which appears as RegWFT in Table II, named with respectto the regularity that is with the signal flow graph) wouldof course decrease size of the circuit as the componentsare re-used by making use of butterfly circuits. However,the power dissipation of this circuit would be huge as thebutterfly circuits will consume too much power along withmany registers and multiplexers. That is in fact why ourapproach both reduced the size of the circuit and decreased thepower consumed at the same time. Our approach, as we namedit PipelinedWFT in Table II, appears to have a superiority overthe other conventional methods.V. CONCLUSION AND FUTURE WORKIn this paper a novel approach to pipeline the structure the 5-point WFT is shown. The novel approach makes use of ReMBand the rest of the circuit utilizes only 3 complex adders and3 complex subtractors with several registers and multiplexersattached to the design. The ReMB itself is composed of 3multiplexers and 3 real adders only. The savings over theapproaches taken from the open literature is obvious. We haveemployed an in-house design tool to estimate the cost of thenovel approach. We have observed that the novel approachconsumes lower power and occupies a smaller area on thecircuit compared to other possible solutions to realize a 5-point WFT circuit. The work we have presented here canbe expanded to WFTs with different sizes and a generalizedapproach applicable to all WFT sizes can be proposed, whichwill be aimed at a later study. Although we have implementedthe circuit on FPGA, the realization of the circuit on a reallife chip solution is also aimed as later research objective.ACKNOWLEDGMENTThe authors would like acknowledge Dr. Suleyman SirriDemirsoy, Altera Corporation, United Kingdom, for the con-structive discussions on the reconfigurable multiplier blocks.REFERENCES[1] S. Winograd, “On Computing the Discrete Fourier Transform,” Mathe-matics of Compututation, pp. 175-199, Jan. 1978.[2] C. S. Burrus, Fast Fourier Transforms, Rice University, Texas, 2008.[3] D. Kolba and T. Parks, A prime factor FFT algorithm using high-speedconvolution, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,vol. SP-29, pp. 281294, Aug. 1977.[4] W. Wyatt-Millington, S. Shepherd, and S. Barton, “A pipelined im-plementation of the Winograd FFT for satellite on-board multi-carrierdemodulation,” Wireless Pers. Commun., vol. 2, no. 4, pp. 321334, 1995.[5] E. H. Wold and A. M. Despain, “Pipeline and parallel-pipeline FFTprocessors for VLSI implementations,” IEEE Trans. Comput., vol. C-33, no. 5, pp. 414426, May 1984.[6] K. R. Rao, D. N. Kim, and J. J. Hwang, Fast Fourier Transform:Algorithms And Applications. Springer, 2010.[7] R.E. Blahut, Fast Algorithms for Digital Signal Processing. Addison-Wesley, 1985.[8] S. S. Demirsoy, I. Kale, and A. G. Dempster, Reconfigurable multiplierblocks: Structures, algorithm and applications, Circuits, Syst. SignalProcess., vol. 26, no. 6, pp. 793827, Dec. 2007[9] S. S. Demirsoy, I. Kale, and A. G. Dempster, ”Synthesis of reconfig-urable multiplier blocks: Part I fundamentals,” in Proc. IEEE Int. Symp.Circuits Syst. (ISCAS), 2005, pp. 536539[10] S. S. Demirsoy, I. Kale, and A. G. Dempster, ”Synthesis of reconfig-urable multiplier blocks: Part II algorithm,” in Proc. IEEE Int. Symp.Circuits Syst. (ISCAS), 2005, pp. 540543[11] N. Aghaee and M. Eshghi, “A Pipelined Architecture for a 20-pointPFA,” in Proc. TENCON 2006, Nov. 2006, pp. 1-4.[12] J. Chen, J. Hu, and S. Li, “High Throughput and Hardware EfficientFFT Architecture for LTE Application,” in Proc. IEEE WCNC, Apr.2012, pp. 826-831.[13] M. D. Macleod, “Multiplierless Winograd and Prime Factor FFT Imple-mentation,” IEEE Trans. Signal processing, vol. 11, no.9, Sept. 2004.

The Design of Low Complexity Low Power Pipelined Short Length Winograd Fourier Transforms

Adem Coskun

Izzet Kale

Richard C. S. Morling

Robert Hughes

Stephen Brown

Piero Angeletti

Crossref

The design of low complexity low power pipelined short length Winograd Fourier transforms

https://westminsterresearch.westminster.ac.uk/download/56b53a0ee50461f5f91d1926faba794775f5d2fac6eaca93264b50f2cb318798/207001/bare_conf-1.pdf

The Design of Low Complexity Low Power Pipelined Short Length Winograd Fourier Transforms

Abstract

Similar works

Full text

Available Versions

WestminsterResearch

Crossref