학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 서종모.Applications to measure accurate time intervals of sub-nano second resolution become popular as sensor and detector technology develops rapidly in the field such as nuclear physics, bio-medical nuclear medicine diagnosis (PET, gamma cameras), time-of-flight measurement and range finding area. As a result, a demand is increasing for digital pulse-processing platform that simultaneously records time of arrival, or time-to-digital converter (TDC), with single-shot accuracy from multiple channels. In this thesis, a multichannel, high timing resolution time-to-digital converter with single-shot accuracy is presented. For low-cost system and flexible reconfiguration, Field Programmable Gate Array (FPGA) is used, and adjustable phase shifted clock scheme is proposed to ensure single-shot accuracy while holding ability to implement multiple channels, which is one of benefits of the phase shifted clock scheme. A TDC system is built based on the proposed architecture. Testing and characterization was done on the system to evaluate the performance of timing accuracy, single-shot capability, timing jitter, Differential Non-Linearity (DNL), Allan deviation (Time base stability) and system throughput.1 Introduction 1
1.1 Time-to-digital Converter 1
1.1.1 Time Interval 1
1.1.2 Dead Time 1
1.1.3 Dynamic Range 2
1.1.4 Differential Non-linearity 3
1.1.5 Dynamic Calibration 5
2 State of the Art 6
2.1 Analog-based TDC 6
2.2 Digital-based TDC 8
2.2.1 Delay Line TDC 7
2.2.2 Inverter Delay Line TDC 11
2.2.3 Carry-chain Delay Line TDC 12
2.2.4 Vernier Delay Line TDC 14
2.2.5 Shifted Clock Sampling TDC 15
3 Implementation 18
3.1 Implementation Objectives 19
3.2 Architecture 20
3.2.1 Compensator 21
3.2.2 Routing for multiple channels 22
3.2.3 FPGA selection 23
3.3 The System Design 24
3.3.1 FPGA TDC 26
3.3.1.1 TDC Front-End Module 26
3.3.1.2 Time-stamping Module 27
3.3.1.3 FIFO AXI DMA Master 27
3.3.1.4 Chip2Chip Interface Controller 28
3.3.2 Digital Processing Unit 28
3.3.2.1 Data Bridge Module 29
3.3.3 Scalability 29
3.3.4 System Build 32
3.3.5 PC Software 33
4 Test and Characterization 34
4.1 Timig accuracy 34
4.2 DNL 38
4.3 Time base stability 42
4.4 Throughput 43
5 Discussion 44
Bibliography 45
초록 47Maste
