'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
In this paper, we explain a configurable IPC module
for multimedia MPSoCs, which was implemented in a MPW chip
that include three ARM7 CPU cores. According to the test results
for an M-JPEG and a H.264 decoder, its IPC synchronization
overheads are not more than 1% when the synchronization
period is about 5000 cycles.This work was supported by the IC Design Education
Center (IDEC) in KAIST, and the Seoul R&BD Program
