This paper presents a hardware solution to the
design of general low-density parity-check (LDPC) decoders,
which simplifies the delivery network required by the message
passing algorithm. While many designs of LDPC decoders for
specific classes of codes exist in the literature, the design of a
general LDPC decoder capable of supporting random LDPC
codes is still challenging. The method proposed in this paper
tries to pack different check node (CN) and variable node (VN)
messages in the Tanner graph representation of the LDPC code,
and is therefore called message packing. This method takes
advantage of the fact that for high-rate LDPC’s the CN’s degree
is much larger than the VN’s, and two distinct methods for
delivering the messages to the CNs and VNs are proposed.
Using the proposed interconnection network (IN) results in lower
complexity decoding of LDPC codes when compared to other
designs.Published versio
