Fast Instruction Set Customization

Abstract

This paper proposes an approach to tune embedded processor datapaths toward a specific application, so as to maximize the application performance. We customize the computation capabilities of a base processor, by extending its instruction set to include custom operations which are implemented as new specialized functional units. We describe an automatic methodology to select the custom instructions from the given application code, in a way that there is no need of compensation code or other modifications in the application, simplifying the code generation. By using the ArchC architecture description language, fast compilation and simulation of the resulting customized processor code are achieved, considerably reducing the turnaround time required to evaluate the best set of custom operations. Experimental results show that our framework provides large performance improvements (up to 3.6 times), when compared to the base general-purpose processor, while significantly speeding up the design process.5358Arnold, M., Corporaal, H., Designing domain-specific processors (2001) CODES, pp. 61-66Atasu, K., Pozzi, L., Ienne, P., Automatic application-specific instruction-set extensions under microarchitectural constraints (2003) DAC, pp. 256-261Brisk, P., Kaplan, A., Kastner, R., Sarrafzadeh, M., Instruction generation and regularity extraction for reconfigurable processors (2002) CASES, pp. 262-269Cheung, N., Parameswaran, S., Henkel, J., INSIDE: Instruction selection/identification & design exploration for extensible processors (2003) ICCAD, pp. 291-297Choi, H., Kim, J., Yoon, C., Park, I., Hwang, S., Kyung, C., Synthesis of application specific instructions for embedded DSP software (1999) IEEE Transactions on Computers, 48 (6), pp. 603-614Clark, N., Zhong, H., Tang, W., Mahlke, S., Automatic design of application specific instruction set extensions through dataflow graph exploration (2003) International Journal of Parallel Programming, 31 (6), pp. 429-449Garey, M., Johnson, D., (1979) Computers and Intractability -A Guide to the Theory of NP-completeness, , Freeman and COGoodwin, D., Petkov, D., Automatic generation of application specific processors (2003) CASES, pp. 137-147Guthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R., Mibench: A free, commercially representative embedded benchmark suite (2001) WWC, pp. 3-14Hennessy, J., Patterson, D., Goldberg, D., (2002) Computer Architecture: A Quantitative Approach, , Morgan Kaufmann PublishersHuang, I., Despain, A., Synthesis of application specific instruction sets (1995) IEEE TCAD, 14 (6), pp. 663-675Kastner, R., Kaplan, A., Memik, S.O., Bozorgzadeh, E., Instruction generation for hybrid reconfigurable systems (2002) ACM TODAES, 7 (4), pp. 605-627La Rosa, A., Lavagno, L., Passerone, C., Hardware/software design space exploration for a reconfigurable processor (2003) DATE, pp. 570-575Lee, C., Potkonjak, M., Mangione-Smith, W., MediaBench: A tool for evaluating and synthesizing multimedia and communication systems (1997) MICRO, pp. 330-335Muchnick, S., (1997) Advanced Compiler Design and Implementation, , Morgan Kaufmann PublishersRigo, S., Araujo, G., Bartholomeu, M., Azevedo, R., ArchC: A SystemC-based architecture description language (2004) 16th Symposium on Computer Architecture and High Performance Computing (SBAC), , http://www.archc.org, Accepted for publication at theStallman, R., (2002) GNU Compiler Collection InternalsSun, F., Ravi, S., Raghunathan, A., Jha, N., Custom-instruction synthesis for extensible-processor platforms (2004) IEEE TCAD, 23 (2), pp. 216-228Van Praet, J., Goossens, G., Lanneer, D., De Man, H., Instruction set definition and instruction selection for ASIPs (1994) Proceedings of the 7th International Symposium on High-level Synthesis, pp. 11-1