The design and physical implementation of field-programmable gate arrays (FPGAs) is a lengthy and expensive process that must be repeated for each new semiconductor technology. Prior FPGA generators have automated some of this process, but have not included the heterogeneous elements FPGA user designs rely on. We augment an existing FPGA RTL generation framework built into the open-source VTR/VPR FPGA CAD suite with heterogeneous functional blocks and carry chains. VTR is leveraged to provide programming support for the new heterogeneous elements. A synthesis methodology is detailed which implements the generated FPGA RTL source in the FreePDK45 process technology. We compare the performance and area of a generated Stratix IV-style FPGA with carry chains, DSPs, and BRAMs against a commercial Stratix IV device. The average area and performance gap observed between the fully synthesizable and commercial fabrics is 2.2x and 2.9x, respectively.M.A.S
