Detailed within this paper is investigation of using low temperature processes to activate dopant in silicon. Parameters studied include breakdown voltage, turn-on voltage, leakage current, and ideality factor. Strong correlation was seen between the temperature of activation and both the ideality factor and leakage current. Breakdown voltage seemed constant except for the highest temperature processing. Turn-on voltage seemed to change for boron activation, but not for phosphorus activatio

Watson, Geoff E

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Watson, Geoff E. 24th Annual Microelectronic Engineering Conference, May 2006 7Junction Integrity for Low TemperatureDopant Activation in SiliconGeoff E. WatsonAbstract—Detailed within this paper is investigation of usinglow temperature processes to activate dopant in silicon.Parameters studied include breakdown voltage, turn-onvoltage, leakage current, and ideality factor. Strongcorrelation was seen between the temperature of activation andboth the ideality factor and leakage current. Breakdownvoltage seemed constant except for the highest temperatureprocessing. Turn-on voltage seemed to change for boronactivation, but not for phosphorus activationIndex Teriizs—Doping, electrical activation, semiconductorprocess modeling, low temperature processing.I. INTRODUCTIONIntrinsic silicon as a semiconductor lacks the conductivityto allow for circuits to operate. This i correcte by theaddition of dopants that increase the conductivity. Dopantsare divided into two subgroups: p-type and n-type. Then-type dopants, such as Phosphorus or Arsenic, whenelectrically activated in the silicon provide extra electronswhich allow the silicon to conduct electricity. The p-typedopants, such as Boron or Gallium, remove electrons whenactivated and the resulting “hole” allows the conduction ofelectricity as well.However, in order for the dopants to becomeelectrically activated, the silicon must undergo a thermalprocess. In the case of thin film transistors where silicon isfound connected to an insulating glass, there are materialconstraints that must be considered. For example, ComingIncorporated produces a glass that has many desirablecharacteristics for thin film transistors. The negativequalities of this glass, however, include its low temperaturestrain point of approximately 660°C. While this isseemingly a high temperature, a comparison with theactivation processing temperatures around 900°C to 1100°Cshows that the glass would be raised far above its strain pointcausing irreparable damage to the glass.Having devised a method of activating the dopant at atemperature of 600°C, there are still concerns as to how thisaffects the electrical devices. This study attempted tocharacterize the effects of lowering the temperature forManuscript received May 20, 2006. This work was supported in part bythe Rochester Institute of Technology.G. H. Watson is with the Rochester Institute of Technology, Rochester,NY 14623 USA (e-mail: gew3076@rit.edu).dopant activation as it relates to several differentcharacteristics found in diodes.II. THEORYA. Low Temperature ActivationIn order for the dopant atom to become electricallyactivated, it must be substituted in to the silicon lattice inplace of a silicon atom. Normal anneal processes do this byincreasing the temperature of the activation step. The use ofthe higher temperatures in the case of the specified CorningInc. glass is impossible as it would damage the glass byraising the temperature over the strain point.An alternative to raising the temperature of the processrequires a look into why the elevated temperature wasthought necessary. In modern processing, silicon atomsmust be substituted for dopant atoms. This substitutionrequires energy. One way to provide this energy is byelevating the temperature. This temperature increaseprovides energy for the silicon to leave the lattice sitewherein the dopant atom is placed. The temperatureincrease, therefore, is only required to remove the siliconatom from the lattice site and place the dopant atom in thatsame site.The alternative processing is to destroy the silicon latticebefore attempting the activation. This amorphization of thelattice allows the temperature increase to be used to rebuildthe lattice using whatever atoms are nearby. After ionimplanting the dose of dopant atoms, the concentrationallows the energy from the temperature to activate thedopant atoms while simply rebuilding the lattice. Thetemperature required for this is much lower than the standardprocessing requiring only 600°C to activate the dopant.B. Amorphizing the LatticeAs it happens, the implanting of dopant atoms creates anamount of implant damage which is amorphization of thesilicon. For phosphorus implantation, the atoms beingimplanted have enough mass to create a large amount ofamorphization. They are said to self-amorphize the lattice.However, boron atoms, because of their small mass, whenimplanted create very little damage to the lattice. For thisreason, another element must be used to create the damagedesired. For ease, fluorine is used to do this damage. This isconvenient because fluorine is another species of elementlocated in the source for the boron dopant. Boron trifluoride,BF3, is the gas used by the ion implanter to provide theboron. Simply turning a dial allows the implantation of theWatson, Geoff E. 24th Annual Microelectronic Engineering Conference, May 2006 8fluorine as well. The fluorine has more mass which providesgreater implant damage. Lastly, the fluorine does not affectthe electrical properties of the implanted silicon making it anideal choice.111. EXPERIMENTAL PROCEDUREA. Diode CreationTo begin this processing, both p-type and n-type waferswere acquired. The resistivity of the p-type wafers was 15 to25 ≤2-cm and the resistivity of the n-type wafers was 10 to25 ~2-cm. The wafers began with an RCA clean using thestandard RIT RCA clean process. A pad oxide was thengrown on the wafers in the Bruce furnace. The recipe usedwas Furnace Recipe 250 which targeted 500A. Followingthis, well implants were performed on the Varian 350D Ionimplanter. For the n-type wafers, phosphorus was implantedat a dose of 5.5x1012 cm2 at an energy of 100 keV. For thep-type wafers, boron was implanted at a dose of 6.0x1012cm2 at an energy of 55 keV. A diffusion step was performedfor the well drive and a field oxide was grown using FurnaceRecipe 112. The field oxide target was 5000 A.Level 1 lithography was then performed. Two die on eachwafer were shot with the NWELL RIT BJT mask to setalignment marks. The rest of the die were shot with theBASE RIT BJT mask. Defaults were used for all of theexposure parameters. To remove the oxide from thepatterned areas, a 12 minute etch was performed in 10:1buffered oxide etch. This was followed by a deionized waterrinse for 5 minutes. The resist was stripped using a solventstrip and an RCA clean was performed to remove anyresidual organics. Furnace Recipe 311 was then used togrow 1000 A of oxide to be used as an implant mask.The backside of the wafers were implanted to improve thecontact between the aluminum. N-type wafers wereimplanted with phosphorus at a dose of lx 1015 cm2 with anenergy of 92 keV. P-type wafers were implanted with boronat a dose of 4x1015 with an energy of 34 keV. FurnaceRecipe 272 was used to anneal the backside implants. Thefrontside of the wafers were then implanted to create theactive area. For the n-type wafers, fluorine was firstimplanted at a dose of 3x1015 cm2 with an energy of 75 keVto amorphize the surface. Boron was then implanted at adose of4x1015 cm2. For the p-type wafers, phosphorus wasimplanted at a dose of 4x1&5 with an energy of 92 keV.The experimental split was performed at the frontsideanneal. The processing conditions can be found in Figure 1.The recipes used were Furnace Recipes 273 through 279.Contact cut lithography was then performed using theCONTACT CUT RIT BJT mask and all the defaultparameters for exposure. The contact cut etch wasnerformed in the same 10:1 buffered oxide etch for 2.25N-type Wafers P-type Wafers600C 1 hr 600oC 1 hr600oC 2 hr 600oC 2 hr700oC 1 hr 700oC 1 hr800oC 1 hr 800oC 1 hr900oC 1 hr 900oC 1 hrl000oC 30 mm l000oC 30 mmllOOoC 10mm llOOoC 10mmFigure 1: Treatment Combinationsminutes. A 5 minute deionized water rinse followed. Theresist was stripped with a solvent strip chemistry again. AnRCA clean was then performed to remove residual organicsfollowed by a 30 second HF dip in 50:1 HF acid to removeany native oxide.Aluminum was evaporated on the frontside of the wafersat a target thickness of 7500 A. Base pressure for theevaporation was 4 with an energy of 92 keV.The experimental split was performed at the frontsideanneal. The processing conditions can be found in Figure 1.The recipes used were Furnace Recipes 273 through 279.Contact cut lithography was then performed using theCONTACT CUT RIT BJT mask and all the defaultparameters for exposure. The contact cut etch wasperformed in the same 10:1 buffered oxide etch for 2.25minutes. A 5 minute deionized water rinse followed. Theresist was stripped with a solvent strip chemistry again. AnRCA clean was then performed to remove residual organicsfollowed by a 30 second HF dip in 50:1 HF acid to removeany native oxide.Aluminum was evaporated on the frontside of the wafersat a target thickness of 7500 A. Base pressure for theevaporation was 4.6x106 Torr. The metal was patternedusing the METAL RIT BJT mask and all the defaultparameters for the exposure. The metal etch was performedin the wet aluminum etch chemistry using a visual endpointdetection. The etch was completed in 2 minutes. Waferswere rinsed and then inspected to ensure that the metal wascompletely etched. The wafers were solvent stripped anddipped in a pad etch to remove any native oxide. The padetch dip was 10 seconds. Aluminum was then evaporated onthe backside of the wafers. A sinter step was performed inthe Bruce Furnace using Furnace Recipe 41. The finisheddiodes were taken to the test lab for analyzation.B. Electrical TestingTen sites were selected on each wafer. Each site wastested with a forward bias and a reverse bias. For the n-typewafers, the forward bias was from -l V to 2 V using 101steps. The reverse bias for these wafers was from -30 V to IV using 101 steps. For the p-type wafers, the forward biaswas from -2 V to 1 V using 101 steps. The reverse bias forthese wafers was -1 V to 40 V using 101 steps. Current ancvoltage were measured and plotted. The desired parametenwere extracted.Watson, Geoff E. 24thi Annual Microelectronic Engineering Conference, May 2006 9IV. RESULTS AND ANALYSISA. Die-to-die RepeatabilityDie to die repeatability for the n-type wafers (withactivated boron) was quite impressive. Figure 2 shows asample reverse bias curve from the n-type wafers. The chartshows very little variation from die to die. It is the same casewith all of the data from the n-type wafers. The rest of thesecurves can be found in the appendix.The p-type wafers (with activated phosphorus), on theother hand, showed quite a large variation from die to die.This dissimilarity can be seen in Figure 3. The leakagecurrent in the reverse bias for the sample curve spans overorders of magnitude difference. However, the data wasconsistently poor for the p-type wafers regardless ofactivation temperature. Again, the remainder of the curvescan be found in the appendix.B. Treatment Combination ComparisonsFor the comparison between the treatment combinations,the data was simply plotted on the same charts. For then-type wafers, any of the die could have been selectedbecause of the small variation among them. For each wafer,regardless of type, one curve was just selected showing themost desirable characteristics. For example, the curve wasselected that had the lowest leakage current or the bestreverse breakdown voltage. The charts can be found in theappendix.1.E-’OO1.5-011.5-021.5-031.6-044~1.5-051.5-061.5-071.E-081.E-09Voltage (V)Figure 3: Reverse Bias for p-type Wafers BiasAs the devices would be operating at voltages ofapproximately 10 V, the leakage current extracted was doneso at a reverse bias of 10 V for the p-type wafers, and -10 Vfor the n-type wafers. The summary tables in Figure 4 andFigure 5 show that leakage current generally worsens as theanneal temperature decreases, but the anneal time at 600°Chad little impact on the leakage current.The ideality factor showed the strongest correlation to theanneal conditions. The factor approached 1 in both wafertypes. Ranging in values from 1 to 2, the ideality for lowtemperature anneals was closer to 2 and decreased as thetemperature increased. This was expected as lowering theanneal temperature was expected to have a negative effect onthe junction integrity and therefore on the ideality.Breakdown voltages for the n-type wafers appeared to beapproximately the same except for the 1100°C anneal whichfar exceeded the others. For the p-type wafers, the noise inthe data was so great that the breakdown voltage listed is notthat reliable. The turn-on voltage showed very littlewafer-to-wafer variation regardless of wafer type.Leakage Turn-on Breakdown Idealitycurrent at Voltage Voltage Factorn-type 1OVReverseBias600°C lhr 18.4 nA 0.78 V -18.2 V 1.56600°C2hr 81.6nA 0.84V -18.8V 1.36700°C lhr 491 pA 1.05 V -18.8 V 1.05800°Clhr 700pA l.03V -19.2V 1.05900°Clhr 465pA l.O1V -18.5V 1.03l000°C3Omin 409pA l.04V -l9.8V 1.05llOO°ClOmin ll5pA 1.05 V -24.4V 1.02Reverse Bias 110CC for 10 mm1 .006-021.006-031.006-041.006-051.006-061.006-071 .00E-081 .006-09-10 0 10 20 30 40 50Reverse Bias 600C for lhr-35 -30 -25 -20 -15Voltage M-10 -5 0 5Figure 2: Reverse Bias for n-type WafersFigure 4: n-type Wafer Summary DataWatson, Geoff E. 24th Annual Microelectronic Engineering Conference, May 2006 10Leakage Turn-on Breakdown Idealitycurrent at Voltage Voltage Factorp-type wafer 1 0VReverseBias600°C lhr 23.5 jiA -0.85 V 27.7 V 1.78600°C2hr 67.3 jiA -0.80 V 31.4 V 1.54700°C lhr 1.89 tiA -0.80 V 29.3 V 1.38800°C lhr 55.7 nA -0.85 V 28.1 V 1.25900°Clhr l6lnA -1.20V 28.lV 1.331000°C 30mm 14.1 nA -0.75 V 29.3 V 1.341100°ClOmin 219nA -0.85 V 32.6V 1.03Figure 5: p-type Wafer Summary DataV. CONCLUSIONLeakage current and ideality factors are definitelynegatively affected by using low temperature for the annealstep. However, the data shows that the “on” state stillproduces a higher current than the reverse bias “off’ state.The diodes should therefore still be usable if the leakagecurrent can be ignored.VI. ACKNOWLEDGMENTThe author would like to acknowledge Dr. Hirschman forhis assistance in choosing this topic.Watson, Geoff E. 24~ Annual Microelectronic Engineering Conference, May 2006 11n-type wafersVII. APPENDIXCurrent vs. Voltage1.E+OOtEO81.E-1O —___________1.E-12-35 -25 -15 -5 5Voltage (V)Current vs. Voltage1.E+O11.~-o11.E-03~ tE-051.E-07d ~• E-09i.E-i 1 —~ —~-1.E-13-35 -25 -15 -5 5Voltage (V)Forward Bias 600C for 1 hr1.E+001.5-011.E-02< 1.5-031.5-041.E-05~ 1.E-061.5-071.E-081.5-091.5-10-1.5 -1 -0.5 0 0.5 1 1.5 2Voltage (V)Reverse Bias 600C for lhr1.E+001.E-011.0-09-35 -30 -25 -20 -15 -10 -5 0 5Voltage (V)2.5Current vs. Voltage1.E-021.E-031.E-041.E-05 /1~1.E-061.E-071.E-08 —---~~—~1E091.E-1OI.E-il-2 -1 0 1 2 3Voltage (V)ICurrent vs. Voltage1.E-02 —-----.-.-—----~1.E-03 -- _______________1.E-04 - _______I.E-OS -~ ______1.E-06 — ______ ______________1.E-071.E-08 —i.E-09 --35 -25 -15Voltage (V)-5 5Current vs. Voltage1.E-O11. E-03 - _____ ___________________ -_____1. E-051. E-07 —~/1.E-09i.E-li1.E-13-2.E+OO -l.E+OO 0.E-t-OO 1.E+OO 2.E-4-OO 3.E÷OOVoltage (V)Current vs. Voltage1.E+O1 •--— _-_......___. -1.E-O1.E-03i.E-OS1.E-071. E-09i.E-Il1.E-13-2 -i 0 1 2 3Voltage (V)Watson, Geoff E. 24~ Annual Microelectronic Engineering Conference, May 2006 12Current vs. Voltage1.E+oo1.E-021.E-04LE-06I 1.E-081.E-1OLE-12-2.E+OO -1.E+OO OE±OO 1.E+O0 2.E+OO 3.E±0OVoltage (V)Current vs. Voltage1. E+OO1.E-02~ 1.E-04~1 E-1 0 r~r ‘~‘1.E-12-4.E+O1 -3.E+O1 -2.E+01 -5.E+OO 5E+OOVoltage (V)C(2Reverse Bias I000C for 30 mmCC)Forward Bias IIOOC for 10 mm Reverse Bias 1100C for l0rrin1.0+001.0-011.0-021.E-031.5-04~ 1.0-051.0-06C~) 1.5-071.0-081.0-091.0-10to-liVoltage (Il)C(2-1.5 -1 -0.5 0 0.5 1 1.5 2 2.5Voltage (V)-35 -30 -25 -20 -15 -10Voltage (V)-5 0 5Reverse Bias1.0-12-1.5 -1 -0.5 0 0.5 1 1.5 2 2.5Voltage (V)1.E*00 - — —- — - -———— —1 .E-01~1.0-12-35 -30 -25 -20 -15 -10 -5 0 5~Voltage (V)Watson, Geoff E. 241h Annual Microelectronic Engineering Conference, May 2006n-type wafersForward Bias 600C for 2 hr1.OOE+001 .OOE-011.000-02~ 1.000-03~ 1.OOE-041.000-051.000-061.000-071 .OOE-08-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage (V)1.000+001.000-011.000-021 .000-031 .000-041 .OOE-050 1.000-061.000-071 .OOE-081.000-09-2.5 -2 -1.5 -1 -0.5 0 0.5Voltage (V)13Forward Bias 600C for 1 hr Reverse Bias 600C for 1 hr1.000+001.000-011.000-021.00 E-031.000-041.000-051.000-061.000-071 .OOE-081.000-09-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage (‘I)1.000-011.000-021.000-031.OOE-041.000-051.000-061.000-071 .OOE-08-10 0 10 20 30 40 50Voltage (V)Reverse Bias 600C for 2 hr1.000-011 .OOE-02~. 1.000-031,000-041 .OOE-051.000-06Forward Bias 700C for 1 hr-10 0 10 20 30 40 50Voltage (V)Reverse Bias 700C for 1 hrz01.5 -10 0 10 20 30 40 50Voltage (V)Watson, Geoff E. 24~ Annual Microelectronic Engineering Conference, May 2006 14Forward Bias I000C for 30 mm1.00E+001 ,00E-011 .OOE-02— 1 .00E-031.OOE-04C1.OOE-051 .OOE-06I .OOE-071 .OOE-081 .OOE-09~1Forward Bias 800C for 1 hrC0C)1.OOE+00I .OOE-011 .OOE-021 .00E-031 .OOE-04I .OOE-051 .OOE-061 .00E-071 .OOE-08I .OOE-091.OOE-10 —-2.5Reverse Bias 800C for 1 hr-2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage (V)Forward Bias 900C for 1 hr-10 0 10 20Voltage (V)30 40 501.OOE-fOO1 .OOE-011 .OOE-021 .OOE-031.005-041.005-05~ 1.005-06C-) 1.OOE-071 .OOE-081 .OOE-091.005-101.005-11-2.5Reverse Bias 900C for 1 hr-2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage (V)-10 0 10 20 30 40 50Voltage (V)C;Reverse Bias I000C for 30 mmC0C-)-10 30 40 5010 20Voltage (V)i.E *001.E-011.E-021.E-03Z 1.E-041.E-05i.E-OS1.E-071.E-080 1.E-09i.E-bi.E-li1 .E-121.E-13Watson, Geoff E. 24~ Annual Microelectronic Engineering Conference, May 2006Forward Bias 1100C for 10 mm1 .OOE-011 .00E-021.OOE-031 .OOE-041.00E051.000-06~ 1.000-07~ 1.000-081.000-091 .OOE-101.000-111.000-121.OOE-1315Reverse Bias IIOOC for 10 mm1.000-02I .000-03I .OOE-041 .OOE-05C1 .00E-06C-)1.000-071.000-081.000-09-10 0 10 20 30 40 50Voltage (V)-2,5 -2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage (V)Forward Bias Reverse BiasC5,01.5-10 0 10 20 30 40 50Voftage (V) Voltage (V)

Junction Integrity for Low Temperature Dopant Activation in Silicon

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Junction Integrity for Low Temperature Dopant Activation in Silicon

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