Engineered Emitters for Improved Silicon Photovoltaics

Abstract

In 2014, installation of 5.3GW of new Photovoltaic (PV) systems occurred in the United States, raising the total installed capacity to 16.36GW. Strong growth is predicted for the domestic PV market with analysts reporting goals of 696GW by 2020. Conventional single crystalline silicon cells are the technology of choice, accounting for 90% of the installations in the global commercial market. Cells made of GaAs offer higher efficiencies, but at a substantially higher cost. Thin film technologies such as CIGS and CdTe compete favorably with multi-crystalline Si (u-Si), but at 20% efficiency, still lag the c-Si cell in performance. The c-Si cell can be fabricated to operate at approximately 25% efficiency, but commercially the efficiencies are in the 18-21% range, which is a direct result of cost trade-offs between process complexity and rapid throughput. With the current cost of c-Si cell modules at nearly 0.60/W.Thetechnologyiswellbelowthehistoricmetricof10.60/W. The technology is well below the historic metric of 1/W for economic viability. The result is that more complex processes, once cost-prohibitive, may now be viable. An example is Panasonic’s HIT cell which operates in the 22-24% efficiency range. To facilitate research and development of novel PV materials and techniques, RIT has developed a basic solar cell fabrication process. Student projects prior to this work had produced cells with 12.8% efficiency using p type substrates. This thesis reports on recent work to improve cell efficiencies while simultaneously expanding the capability of the rapid prototyping process. In addition to the p-Si substrates, cells have been produced using n-Si substrates. The cell emitter, which is often done with a single diffusion or implant has been re-engineered using a dual implant of the same dose. This dual-implanted emitter has been shown to lower contact resistance, increase Voc, and increase the efficiency. A p-Si substrate cell has been fabricated with an efficiency of 14.6% and n-Si substrate cell with a 13.5% efficiency. Further improvements could be made through the incorporation of a front-surface field, surface texturing and nitride ARC

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