Very-Large Scale Integration (VLSI) is the problem of arranging components on the surface of a circuit board and developing the wired network between components. One methodology in VLSI is to treat the entire network as a graph, where the components correspond to vertices and the wired connections correspond to edges. We say that a graph G has a rectangle visibility representation if we can assign each vertex of G to a unique axis-aligned rectangle in the plane such that two vertices u and v are adjacent if and only if there exists an unobstructed horizontal or vertical channel of finite width between the two rectangles that correspond to u and v. If G has such a representation, then we say that G is a rectangle visibility graph.
Since it is likely that multiple components on a circuit board may represent the same electrical node, we may consider implementing this idea with rectangle visibility graphs. The rectangle visibility number of a graph G, denoted r(G), is the minimum k such that G has a rectangle visibility representation in which each vertex of G corresponds to at most k rectangles. In this thesis, we prove results on rectangle visibility numbers of trees, complete graphs, complete bipartite graphs, and (1,n)-hilly graphs, which are graphs where there is no path of length 1 between vertices of degree n or more
