The evaluation of a metal gate PMOS op amp, including verification of the integrated circuit layout and a check of the PMOS design rules, was performed. The SPICE deck was modified to include a mask error which was discovered and the resulting simulation compared to DC measurements. The results indicate design errors at the input stage of the op amp. Open loop simulations performed by SPICE also show design errors within the gain stage. Suggestions for a more thorough investigation of the design are given
