The use of CMOS-based transistors to implement digital logic is the prevalent means of modern computation. It is, however, not the only means. Advances in nano-science and engineering demonstrate that nano-scale integrated circuits are in fact a viable technology for computation. The dominant means for information propagation in these devices is quantum tunneling - a phenomenon that is not wholly compatible with current design techniques. This paper is an explanation of one process used to both design and simulate digital logic circuits utilizing the topology of the hypercube. The aim of the paper is to demonstrate the ease of designing and implementing a streamlined design environment and to demonstrate the utility that such an environment affords the designer. The hypercube topology is used as the dominant example for constructing 3D circuits. In this topology, each device is required to operate as a doubly gated switch and computation is performed utilizing a concept similar to pass-gate technology. The paper details the software required to generate the logic circuit and the means of simulation. Each device of the structure is modeled using a non-linear state-space representation. The paper concludes with two examples of implementable technologies: single-electron transistors (wrap-gate structures with quantum dots), and endohederal fullerenes acting as gate switches
