Advanced crystal growth techniques enable novel devices and circuit designs to further scale and integrate heterogeneous structures for CMOS, MEMS/NEMS, and optoelectronic applications. In particular, nanowires (NW) are among the promising structures derived from these developments. Research has demonstrated the utility of NWs as a channel material for gate-all-around transistors, high sensitivity biological/chemical sensors, photodetectors, as well as a whole spectrum of LEDs and lasers. However, NW based devices are not without their fabrication challenges. Relatively simple structures for CMOS or MEMS/NEMS processes are difficult to reproduce when many NW based devices rely on a dropcast process. This thesis demonstrates a method for producing Germanium on Nothing (GON) NW arrays on a Si substrate that forgoes dropcasting and, instead, creates NWs via selective material removal methods commonly utilized by industry. GON NW arrays are formed through the sequential use of E-beam lithography, selective wet chemical etching, and reactive ion etching. Global oxide thinning in BOE leaves a thin masking layer that protects the underlying Si, preventing etching in a TMAH solution. GON regions are defined by E-beam lithography and are subject to a RIE which creates release points in the remaining SiO2. Unmasked Si is then etched by a TMAH solution, undercutting the Ge lines, leaving an array of suspended Ge wires. NW dimensions are reached by thinning the Ge wire diameter with a H2O2 solution. NWs with ~50 nm diameters and ~ 200 nm lengths, as well as 10 [micron] by 10 [micron] membranes of Ge/SiO2, have been demonstrated in this thesis
