This paper presents a fully-integrated 0.18 mu m CMOS low drop-out (LDO) regulator designed to drive on-chip low power frontend sensor nodes. The proposed LDO is based on a simple telescopic amplifier stage with internal cascode compensation driving a PMOS pass-device, providing a high precision 1.8 V output voltage for input voltages from 3.6 V to 1.92 V up to a 50 mA load current with only 22 mu A quiescent current. Line and load regulation are respectively better than 0.017 mV/V and 0.003 mV/mA, while recovery times are below 4 mu s over a (-40 degrees C, 120 degrees C) temperature span

Calvo, B.

Marquez, A.

Martinez, P.A.

Medrano, N.

Perez-Bailon, J.

Sanz-Pascual, M.T.

English

Repositorio Universidad de Zaragoza

 Procedia Engineering  168 ( 2016 )  1655 – 1658 Available online at www.sciencedirect.com1877-7058 © 2016 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).Peer-review under responsibility of the organizing committee of the 30th Eurosensors Conferencedoi: 10.1016/j.proeng.2016.11.483 ScienceDirect30th Eurosensors Conference, EUROSENSORS 2016 A Fully-Integrated CMOS LDO Regulator for Battery-Operated  On-Chip Measurement Systems J. Pérez-Bailóna,*, A. Márqueza, B. Calvoa, N. Medranoa, P.A. Martíneza,  M.T. Sanz-Pascualb a Group of Electronic Design – I3A University of Zaragoza, Zaragoza 50009, Spain b Instituto Nacional de Astrofísica, Óptica y Electrónica INAOE, Tonantzintla, Puebla, México Abstract This paper presents a fully-integrated 0.18 µm CMOS low drop-out (LDO) regulator designed to drive on-chip low power front-end sensor nodes. The proposed LDO is based on a simple telescopic amplifier stage with internal cascode compensation driving a PMOS pass-device, providing a high precision 1.8 V output voltage for input voltages from 3.6 V to 1.92 V up to a 50 mA load current with only 22 µA quiescent current. Line and load regulation are respectively better than 0.017 mV/V and 0.003 mV/mA, while recovery times are below 4 μs over a (-40 ºC, 120 ºC) temperature span.  © 2016 The Authors. Published by Elsevier Ltd. Peer-review under responsibility of the organizing committee of the 30th Eurosensors Conference. Keywords: Voltage regulator; low drop-out (LDO); CMOS design; System-on-Chip (SoC); power management; portable sensing devices. 1. Introduction The portable sensor market is pushing towards complete system-on-chip (SoC) solutions. To achieve this, one increasingly important subsystem, especially in autonomous battery powered sensing devices is the power management unit (Fig.1 a), where low drop-out regulators play a key role: they must deliver a stable power supply Vout under variations of load current ILoad and battery voltage VBAT. This work presents the design in a 0.18 ?m CMOS technology of a fully integrated LDO regulator to power both the read out and actuation electronics of a battery-compatible front-end sensor interface based on phase-sensitive detection (PSD) [1]. Accordingly, design specifications   * Corresponding author. Tel.: +34976761240. E-mail address: 610686@unizar.es © 2016 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).Peer-review under responsibility of the organizing committee of the 30th Eurosensors Conference1656   J. Pérez-Bailón et al. /  Procedia Engineering  168 ( 2016 )  1655 – 1658   Fig. 1. (a) Block diagram of a typical power delivery system; (b) Conventional topology of a LDO voltage regulator. are: an output voltage of 1.8 V from a 3.6 V – 2.1 V battery-compatible input voltage range, with a maximum load current of 50 mA over a 50 pF maximum capacitive load. Besides, it must comply with the two critical requirements of portable systems, i.e. reduced area and quiescent current, while maintaining good regulating performance, stability and fast response times, a challenging task with an on-chip approach avoiding the use of an external compensation capacitor [2]. The paper is organized as follows. Section 2 presents the proposed CMOS LDO architecture satisfying the specifications given by our target application. Section 3 summarizes the main achieved performances. Finally, conclusions are drawn in Section 4. 2. LDO Architecture Fig. 1 b shows the classical topology of a CMOS LDO regulator, which provides a stable voltage Vout from a variable power supply VBAT to properly bias the corresponding electronic system, modeled by a load current ILoad and a load capacitor CLoad. It consists of a voltage reference Vref, an error amplifier (EA), a PMOS transistor as the pass element between the variable voltage VBAT and the stable voltage Vout, and a resistive feedback network Rfb1 – Rfb2 [3]. The circuit operates as follows: the feedback network samples the output voltage Vout; the error amplifier compares this feedback signal Vfb with a bandgap reference voltage Vref, and generates an error signal that continuously drives the gate of the pass transistor to keep a constant Vout independently of VBAT and ILoad:  ???? ? ?? ? ????????? ???? (1) Following this scheme, the proposed LDO voltage regulator is shown in Fig. 2. It has been implemented in the UMC 0.18 μm 1P-6M CMOS technology. The design of the main blocks at transistor level is next discussed, except for the voltage reference Vref, which is provided by an external 1.2 V bandgap reference.  2.1. Pass Transistor Pass transistor size is a critical parameter determined by the maximum load current and the minimum dropout voltage Vdo = (Vin,min - Vout) requirements, resulting in a device requiring very large silicon area. With our specifications, its size results (W/L) = (9480 μm / 0.34 μm) to keep the transistor working in saturation for  ILoad = 50 mA with Vdo = 300 mV. 2.2. Feedback Network Assuming, for ILoad = 0, a quiescent current through the PMOS pass transistor IRfb = Vout / (Rfb1 + Rfb2) =10 μA to keep bounded the overall static power consumption, and with a 1.8 V output voltage (eq. 1), it is obtained Rfb1 = 60 kΩ and Rfb2 = 120 kΩ. These resistances are implemented as active resistances using three identical PMOS transistors in diode configuration to optimize area: this solution reduces in a factor 3 the conventional passive solution using a high resistive polysilicon layer given by the technology (R□ = 1039 Ω/square, W = 1 μm, L = 166.1 μm). 1657 J. Pérez-Bailón et al. /  Procedia Engineering  168 ( 2016 )  1655 – 1658 2.3. Error Amplifier The EA must meet as specifications a high DC open loop gain, as the LDO line and load regulation are inversely proportional to the EA gain, and a low static current to minimize the power consumption [4]. The minimum gain required in order to have 0.1% output voltage accuracy is 60 dB. Besides, a maximum EA current budget of 10 µA is set as design specification. The configuration used is a telescopic OTA that provides a gain above 75 dB over all the operating 3.6 V – 2.1 V supply with a simple single-stage architecture, also characterized by a GBW > 330 kHz and PM = 90 ? for a load capacitor determined by the parasitic pass transistor Cgs (12 pF – 20 pF). 2.4. Compensation Network To obtain an on-chip solution it is necessary the use of internal compensation techniques. In this work, cascode compensation, using a single Cc = 8.5 pF capacitor as shown in Fig. 2, is adopted, thus achieving higher speed and power supply rejection (PSR) compared to the commonly used Miller compensation. 2.5. Transient behavior improvement To enhance the transient behavior, a dynamically biased current sink path formed by a quasi-floating gate transistor MSINK is added, which is only active when the load current varies from high to low, helping to discharge the path formed by (Rfb1 + Rfb2) and CLoad. 3. Simulation Results The regulation region ranges from Vin = 1.92 V to 3.6 V, i.e. the LDO has a dropout voltage of 120 mV over a  (-40 ºC to 120 ºC) span. Fig. 3 shows the line regulation for ILoad = 50 mA (worst case) and Fig. 4 shows the load regulation for VBAT = 2.1 V (worst case). Fig 5 shows the open loop frequency performance over all the operating conditions. Fig. 6 shows the full load transient response, with and without the proposed enhancement circuit. Table 1 summarizes the main performances of the proposed LDO regulator compared to previous implementations with similar specifications [2, 5, 6]. Our proposal attains significantly better regulation performance while keeps similar power, size and time response paramenters.  Fig. 2. Schematic of the proposed CMOS LDO.  Fig. 3. Static line regulation, ILoad = 50 mA.  Fig. 4. Static Load regulation, VBAT = 2.1 V. 1658   J. Pérez-Bailón et al. /  Procedia Engineering  168 ( 2016 )  1655 – 1658  Fig. 5. Open-loop frequency response, VBAT = 2.1 V.  Fig. 6. Full load transient w/o and with current sink path, VBAT = 3.6 V.  Table 1. Comparison of CMOS capacitor-less LDO performances. Parameter This work, sim [2], 2007, exp [5], 2011, exp [6], 2014, sim post-layout CMOS Technology (µm) 0.18 0.35 0.35 0.18 Vin (V) 1.92 – 3.6 3 1.642 – 5 2.1 – 3.3 Vout (V) 1.8 2.8 1.5 1.8 Vdo (mV) @ ILoad,max 120 @ 50 mA 200 @ 50 mA 142 @ 100 mA 350 @ 70 mA Iq (µA) 22 65 27 47 CLoad (pF) 50 100 100 50 Line Regulation (mV/V) 0.017 ~23 1.046 0.24 Load Regulation (mV/mA) -0.003 ~0.56 0.0752 0.714 Full load settling time (µs) 4 15 1 (IL:0 to 100 mA) 2 PSR (dB) -62 @ 1 kHz -57 @ 1 kHz 60.6 @ 1 kHz -57 @ 1 kHz 4. Conclusions A high precision low quiescent current LDO regulator to be used in portable sensing devices has been proposed and designed in a 0.18 μm CMOS process. Simulation results of its main static, dynamic and frequency properties validate the applied design strategies, successfully achieving the target specifications to attain a forthcoming SoC CMOS portable PSD measurement system.  Acknowledgements This work has been supported by the project TEC2015-65750-R (MINECO/FEDER, UE). References [1] D. García-Romeo, M. R. Valero, N. Medrano, B. Calvo, S. Celma. A High Performance LIA-Based Interface for Battery Powered Sensing Devices. Sensors-Basel, vol. 10, pp. 25260-25275, Sept. 2015. [2] R. J. Milliken, J.Silva-Martínez and E. Sánchez-Sinencio. Full On-Chip CMOS Low-Dropout Voltage Regulator. IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 1879 1890, Sep. 2007. [3] G. Rincon-Mora and P. Allen. A low-voltage, low quiescent current, low drop-out regulator. Solid-State Circuits, IEEE Journal of, vol. 33, no. 1, pp. 36–44, Jan 1998. [4] B. S. Lee. Technical Review of Low Dropout Voltage Regulator Operation and Performance. Application Report, Texas Instrument (1999). [Online]. Available: www.ti.com/lit/an/slva072/slva072.pdf. [5] C.-. Chen, C.-C.Hung. A fast self-reacting capacitor-less low-dropout regulator. European Solid State Circuits Conference, pp.375–378, 2011. [6] C. Ventura-Arizmendi, M.T. Sanz-Pascual, B. Calvo. A 0.18um CMOS Low-Dropout Voltage Regulator for Battery-Operated Sensing Systems. Proc. of the XX Workshop Iberchip, 2014. 

A Fully-Integrated CMOS LDO Regulator for Battery-Operated On-Chip Measurement Systems

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A Fully-Integrated CMOS LDO Regulator for Battery-Operated On-Chip Measurement Systems

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