Triger, S

This thesis documents research to improve tolerance to faults of an embedded parallel network. This resulted in the development of two building blocks of a novel embedded communications system with enhanced fault detection and recovery. 

 

A review of embedded inter-processor communications was initially performed. The research aimed to expand the potential of embedded parallel systems in three main areas: improving bi-directional throughput; implementing a distributed fault detection, isolation and recovery mechanism; and the implementation of hardware virtual channels utilising Context Addressable Memory (CAM) to reduce processor intervention. 

 

The embedded multiprocessor network comprises off-the-shelf custom hardware message routers. An interface between a StrongArm SA-110 microprocessor and the embedded routing network was developed using VHDL. This was simulated and synthesised, with post-synthesis simulations used as a means of gauging performance. An interface was also developed between a PC and the network, utilising the PCI bus standard for communication. The research resulted in a fully operational hardware prototype, whose results were compared and contrasted with both the previous non-fault tolerant PCI interface and theoretical expectations. 

 

The routers, StrongArm processors, PCs and their respective interfaces form the building blocks of a robust, embedded network with improved tolerance to faults. The StrongArm and PCI interfaces allow RISC and general-purpose processors to operate as processor nodes in the same network, thus increasing system flexibility and applications. The possibility of adapting the interface design to other processors offers further possible increases in system flexibility. The new protocol allows a much greater degree of tolerance to faults in the system, reducing the dependence on external intervention in the event of network failure

Interfaces for embedded parallel multiprocessor networks

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