Journal ArticleThe total ionizing dose characterization of the radiation-hardened implementation of a novel architecture for high-performance, energy efficiency FFT engines is presented. Simulations and test chip measurement results indicate that a radiation-tolerant 1024-point FFT  based on this architecture will achieve an efficiency  of 120 nJ/Unit-Transform and 2 ms throughput. The proof-of-concept chip shows a total ionizing dose hardness of 1 Mrad (SiO2)

Barnhart, D

Stevens, Kenneth

English

The University of Utah: J. Willard Marriott Digital Library

TOTAL IONIZING DOSE CHARACTERIZATION OF A COMMERCIALLY FABRICATEDASYNCHRONOUS FFT FOR SPACE APPLICATIONS*D. Barnhart, P. Duggan, B. SuterAir Force Research LaboratoryC. BrothersAir Force Institute of TechnologyK. StevensIntel Corporation                                                * This effort is sponsored, executed and managed by the United States Air Force, Air Force Material Command,Air Force Research Laboratory, Space Vehicles (Kirtland AFB, NM) and Sensors (Wright-Patterson AFB) Direc-torates.ABSTRACTThe total ionizing dose characterization of theradiation-hardened implementation of a novelarchitecture for high-performance, energy ef-ficiency FFT engines is presented.  Simula-tions and test chip measurement results indi-cate that a radiation-tolerant 1024-point FFTbased on this architecture will achieve an ef-ficiency of 120 nJ/Unit-Transform and 2 µsthroughput.  The proof-of-concept chip showsa total ionizing dose hardness of 1 Mrad(SiO2).INTRODUCTIONDigital signal processing (DSP) is an essen-tial function for a majority of military andcommercial space platforms.  Various DSPand general-purpose processors are avail-able and typically used for this purpose.  Oneof the most common DSP functions is theFast Fourier Transform (FFT).  The Air Forcehas developed a specific architecture for de-signing high-performance, energy efficientFFT integrated circuits (ICs) [1].  Simulationdata indicates that a 1024-point FFT basedon this architecture has a predicted efficiencyof 120 nJ/Unit-Transform and 2 µs through-put [2].  A subset of this architecture was im-plemented in a proof-of-concept chip that wasfabricated on a commercial process using ahardened-by-design gate array [3].  Theproof-of-concept chip has clearly demon-strated a total ionizing dose hardness wellbeyond 1 Mrad (SiO2).BACKGROUNDThe Air Force received a patent on an asyn-chronous, pipelined FFT architecture for im-plementing energy-efficient high-performanceFFT designs in 1997 [1].  We present a proof-of-concept FFT test chip demonstrating asubset of this architecture designed at the AirForce Institute of Technology (AFIT) as partof a thesis effort sponsored by the Air ForceResearch Laboratory (AFRL) [2].  The designof the proof-of concept chip was limited to afour-point FFT (FFT-4) with a fixed-point datapath of 16-bits for each data word in thecomplex domain.The FFT-4 was fabricated on the Hewlett-Packard 0.5 µm (gate oxide thickness of 9.4nm) commercial CMOS process throughMOSIS using a hardened-by-design (HBD)gate library that has been demonstrated andcharacterized previously [3].  This HBD ap-proach is based on the use of annular tran-sistors and guard bands, among other hard-ening approaches, as shown in Figure 1.Gate ContactP-PlusGuard BandN-PlusDrainN-PlusSourceFigure 1. Simplified schematic of a re-entrant n-type transistor [3]The HBD approach offers numerous benefitswith a sacrifice in area.  The re-entrant n-typetransistor eliminates the edge leakage phe-nomenon observed in commercial CMOS cir-cuits in a total ionizing dose (TID) radiationenvironment, which is the predominant failuremechanism. Guard bands are used to elimi-nate the inter-transistor leakage associatedwith the oxide charging under the field oxidebetween adjacent transistors.  The guardbands, in conjunction with proper transistorspacing, serve to suppress single eventlatchup (SEL) by eliminating the parasitictransistor.  The single event upset (SEU) en-ergy threshold is raised by utilizing properlyratioed high drive strength transistor pairs.[2][3]The primary motivation for this approach is toleverage the affordability and availability ofcommercial foundries while achieving a cir-cuit hardened to total ionizing dose and sin-gle event effects.  However, this particulargate array design, including the annular tran-sistor and guard bands, suffers a factor offour area penalty. [3]Initial performance characterization of theFFT-4 reveals an efficiency of 36 nJ/Unit-Transform and a transform throughput of 380ns.  Previous simulations of the FFT-4 pre-dicted an efficiency of 4.25 nJ/Unit-Transformand a throughput of 180 ns [2].  The substan-tial performance discrepancy between simu-lation results and device measurements isreadily justified. The simulation results did notinclude the delays and power consumption ofthe input and output pads or the capacitivelosses from the test chip packaging.  In alarger system these losses will not be real-ized since the FFT engine will be part of alarger DSP system and will be connected allon one die.  Additional simulation results indi-cate that a full FFT-1024 based on this ar-chitecture has a projected efficiency of 120nJ/Unit-Transform and a throughput of 2 µs[2].  Comparing this performance data toother unhardened commercial and researchbased DSP devices reveal a significant per-formance advantage as illustrated in Figure2.PathfinderIILH9124C40SpiffeeCOBRADSP-24AFRL(Rad Hard)1101001000100001 10 100 1000 10000   Faster (FFT Throughput in µs)✁ More Efficient (Efficiency in nJ/U-T)Figure 2. FFT Performance DiagramTable 1 summarizes performance details foreach FFT engine listed in Figure 2. An FFTimplemented with unhardened library cellsusing this architecture would have an evengreater efficiency.Table 1. FFT Comparison TableProcessor Design Feature DatawordSize & TypeVSS(V)FFT-1024through-put(µs)FFT-1024Efficiency(nJ/U-T)Air ForceRad-TolerantResearch FFT16-bitFixed Point 3.3 2 120DSP-24 [5]UnhardenedCommercial DSP24-bitFixed Point 3.3 22 71.8TI C40 [6]UnhardenedCommercial DSP32-BitFloating Point 5.0 1298 5704Spiffee [7]UnhardenedResearch FFT20-bitFixed Point 3.3 30 24.7COBRA [8]UnhardenedResearch FFT23-bitFixed Point 5.0 9.5 71.4LH9124 [9]UnhardenedCommercial DSP24-bitFixed Point 5.0 54 75PathfinderII[10]UnhardenedCommercial DSP32-bitFloating Point 3.3 15.4 60There are several benefits of using the AirForce’ s FFT architecture.  This architectureuses a pipelined approach, reduces globaldata and control bus structures and requiresno shared memory.  Computation of the top-level FFT is executed through a combinationof smaller FFTs and complex multipliers.  Toconserve energy, the entire design is imple-mented in an asynchronous fashion, whichuses local handshaking between functionalblocks, thereby eliminating inefficient globalclock circuitry [4].TOTAL IONIZING DOSE EVALUATIONThe FFT-4 was evaluated for its total ionizingdose response to 20 KeV (average energy)X-rays at the Low-Energy X-Ray (LEXR) fa-cility and to high energy Gamma radiation atthe large area Cobalt-60 (Co-60) source.Five FFT-4 devices were evaluated at eachsource.  Both evaluations adhered to theguidelines set forth in MIL-STD-883, TestMethod 1019.5.  Each source used the samedevice under test (DUT) board and biasingtechnique to ensure the worst-case bias con-dition of the FFT-4.  A pre-irradiation electri-cal performance baseline was taken for alldevices immediately prior to irradiation.  OneFFT-4 irradiated at each radiation source wasannealed under bias for 168 hours at 100 °Cafter the final radiation exposure.The AFRL LEXR facility is a room cell con-taining a Philips X-ray tube, model MCN-165.The beam is filtered by a 0.002” Al sheetplaced 10.0 cm from the source to suppressthe very low energy X-ray spectrum and iscollimated with a 0.500” lead hole collimator.Dosimetry was accomplished at 25.0 cm fromthe source using an ARACOR PIN diode,model number CS-1003.  For this characteri-zation, a dose rate of 92.95 rad(SiO2)/secwas achieved at a distance of 25.0 cm fromthe source for a X-ray tube voltage of 50 kVand a current of 10 mA. The dose rate isspecified in rad(SiO2) due to the fact that Siand SiO2 have different scaling factors forenergy deposition depending on the photonenergy.  At 20 keV, the theoretical energydeposition ratio (Si/SiO2) is approximately1.8. [11]The AFRL Co-60 facility is a panoramic roomcell containing a J.L. Shepherd Type 7810Co-60 source.  The DUT assembly was en-closed in a lead-aluminum box to eliminatethe low energy photons resulting from back-scattering.  Dosimetry was accomplished bya Rad-Cal Model 2025 ion chamber dosime-ter.  A dose rate of 92.3 rad(SiO2)/sec wasmeasured at the DUT at a distance of 8.0 cmfrom the source.The DUT board used was compatible with theHewlett-Packard 82000 integrated circuitevaluation system.  The DUT board has pro-visions for biasing the FFT-4 during irradia-tion.  Bias power was continuously suppliedeither through a hard wired power supplyduring irradiation or a battery during transportbetween the HP 82000 and the radiationsource.  The voltage on the board and cur-rent flowing through the FFT-4 was monitoredduring each irradiation.  The HP 82000 wasprogrammed to evaluate the FFT chip with asuite of test vectors to verify functionality,maximum operating frequency, operating cur-rent, standby current and input leakage cur-rent.  Before each irradiation, the FFT-4 wasinitialized with an input sequence.  Upon thecompletion of the irradiation, a correspondingoutput sequence was read from the FFT-4 toensure that there were no data upsets andthat the circuit remained under bias through-out the irradiation.The results of the total ionizing dose evalua-tion indicate that there are no measurablechanges to the FFT-4’ s performance until alevel of 250 krad(SiO2) is reached.  After thatpoint, a very shallow degradation takes placeuntil the end of the evaluation, which was at1.5 Mrad(SiO2).  At that point, the operatingcurrent only increased to a maximum of 4 mA(3.5%) above the nominal value, dependingon the DUT.  Figure 3 reveals an increase ofthe operating current in response to the totaldose in the LEXR.  Figure 4 shows the oper-ating current response in the Co-60.  Notethat the baseline operating current of mostDUTs was 115 mA, however a few DUTs hada baseline of 117 mA.  This type of varianceis typical in a process run from MOSIS andthe values are all within 2% of each other,which is actually quite exceptional.Figure 3.  Response of Operating Current to TID (LEXR)Figure 4.  Response of Operating Current to TID (Co-60)The other key parameter that was measuredduring the evaluation was the critical pathlengthening.  Due to the fact that the circuit isnot a traditionally clocked (synchronous) cir-cuit, there is no clock frequency that can beadjusted to compensate for slower operationof the circuit.  The computational speed of theasynchronous FFT-4 is based on the inputdata.  Therefore, to determine if there wasany slowing of the device, the longest com-putational cycle (critical path) was comparedto the baseline performance after each expo-sure level.  During the course of the evalua-tion, the critical path lengthened to a maxi-mum of 4 ns above the normal value of 380ns as shown in Figure 5 and Figure 6, for theLEXR and Co-60 sources, respectively.Figure 5. Critical Path Lengthening in Response to TID (LEXR)Figure 6. Critical Path Lengthening in Response to TID (Co-60)The predominant degradation mechanism,which caused the increased leakage currentin this case, is the leakage current throughthe field oxide caused by charge buildup. Theslower response time is due to the build up ofinterface traps, which soften the response ofboth transistor types. HBD techniques canonly minimize these phenomena—they can-not eliminate them entirely.A secondary purpose of this study was tofurther investigate the claim that a low-energyX-ray source can be used to approximate theresults that are seen in a gamma radiationsource in complex CMOS circuits.  To com-pare results from each source, the resultsfrom each source were averaged and thencompared.  Figure 7 compares the responseof the operating current in each source.Figure 8 compares the lengthening of thecritical path.  The response in each source forboth parameters is nearly identical.Figure 7. Comparison of Operating CurrentFigure 8. Comparison of Critical Path DelayFUTURE EFFORTSThe design of an FFT-16 and FFT-64 basedon similar design principles used in the de-sign of the FFT-4 has been completed.  TheFFT-16 will be fabricated on the Massachu-setts Institute of Technology/Lincoln Labora-tory 0.18 µm, fully depleted, silicon-on-insulator (SOI) line using a HBD gate array.It is expected, that the smaller feature sizealong with the reduced capacitance of theSOI fabrication process will further enhancethe efficiency and throughput of the FFT. Inaddition, packaging and I/O efficiency losseswill become less of a factor due to the circuitarea becoming the dominant structure incomparison to the I/O structure.  A full radia-tion environment characterization of the FFT-16 will be accomplished and published.  TheFFT-64 is the last major building block in theimplementation of an FFT-1024.  The designand fabrication of the FFT-1024 is scheduledto take place by the end of 2000.SUMMARY AND CONCLUSIONSThe design of the Air Force’ s FFT architec-ture is presented. The asynchronous natureof the design has enabled high efficiency andthroughput, which yields a significant per-formance improvement over commercial un-hardened DSP designs.  The total ionizingdose response is minimal up to 1 Mrad (SiO2)for both the low-energy X-ray source and theCo-60.  This research is paving the way forthe next generation of high performanceDSPs for space applications.REFERENCES1. Suter, Bruce W. and Kenneth S. Stevens,“Low Energy Consumption, High Perform-ance, Fast Fourier Transform.”  U. S. PatentNumber: 5,831,883, May 1997.2. Barnhart, David J.  An Improved Asyn-chronous Implementation of a Fast FourierTransform Architecture for Space Applica-tions.  MS Thesis, AFIT/GE/ENG/ 99M-01.School of Engineering, Air Force Institute ofTechnology (AU), Wright-Patterson AFB OH,March 1999.3. Brothers, Charles P., et al.  “Radiationhardening Techniques for Commercially Pro-duced Microelectronics for Space Guidanceand Control Applications,” 20th Annual Ameri-can Astronautical Society Guidance andControl Conference.  169-180.  February1997.4. Hauck, Scott.  “Asynchronous DesignMethodologies: An Overview,” Proceedingsof the IEEE,83: 69-93 (January 1995).5. DSP-24, DSP Architectures, VancouverWA.  http://www.dsparchitectures.com6. C40, Texas Instruments, Dallas TX.http://www.ti.com/sc/docs/military/liter/sgyv005c.pdf7. Baas, Bevan M.  “And Energy-EfficientSingle-Chip FFT Processor,” Symposium onVLSI Circuits.  164-165.  June 1996.8. Sunada, Glen, et al.  “COBRA: A 1.2 Mil-lion Transistor Expandable Column FFTChip,” ICCD.  546-550.   1994.9. Sharp LH9124, Sharp Inc.http://nova.stanford.edu/~bbaas/fftinfo.html10.  PathfinderII, Catalina Reasearch, Colo-rado Springs, CO.http://www.catalinaresearch.com/CRItechdata/default.htm11. National Institute of Standards and Tech-nology.http://physics.nist.gov/PhysRefData/XrayMassCoef/cover.html

Total ionizing dose characterization of a commercially fabricated asynchronous FFT for space applications

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Total ionizing dose characterization of a commercially fabricated asynchronous FFT for space applications

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