Journal ArticleA class of integrated circuit design and implementation methodologies is described. These techniques are unique in that they simultaneously model both function and interconnect using cells. These cells are designed such that cell adjacency normally implies interconnection. The absence of an interconnection is explicitly modeled as a wire break between adjacent cells. These methodologies have the potential to greatly simplify and shorten the design process since some design steps are either eliminated or merged with others. They permit near custom layout density while reducing design time over full custom design by up to thirty times and over gate array design by up to four times
