Journal ArticleAsynchronous/Self-timed circuits are beginning to attract  renewed attention as promising means of dealing with  the complexity of modern VZSI designs. Very few analysis techniques or tools are available for estimating their performance. In this paper we adapt the theory of Generalized Timed Petri-nets (GTPN) for analyzing and comparing asynchronous circuits ranging from purely control-oriented circuits to those with data dependent control. Experiments with the GTPN analyzer are found to track the observed performance of actual asynchronous circuits, thereby offering empirical evidence toward the soundness of the modeling approach

Brunvand, Erik L.

Gopalakrishnan, Ganesh

English

The University of Utah: J. Willard Marriott Digital Library

Performance Analysis and Optimization of Asynchronous Circuits Prabhakar Kudva, Ganesh Gopalakrishnan*, Erik Brunvand* Venkatesh Akella Department of Computer Science University of U tab Salt Lake City, UT 84112 Abstract Asynchronous/Self-timed circuits are beginning to at-tract renewed attention as promising means of dealing with the complexity of modern VLSI designs. Very few anal-ysis techniques or tools are available for estimating their performance. In this paper we adapt the theory ofGeneral-ized Timed Petri-nets (GTPN)for analyzing and comparing asynchronous circuits rangingfrom purely control-oriented circuits to those with data dependent control. Experiments with the GTPN analyzerarefoundto track the observed per-formance of actual asynchronous circuits. thereby offering empirical evidence towards the soundness of the modeling approach. 1 Introduction Asynchronous (or Self-timed [13]) circuits are begin-ning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. One of the widely touted advantages of asynchronous circuits is that they exhibit better average case performance (here. and elsewhere, performance means overall speed or through-put). In this paper. we propose performance analysis tech-niques for asynchronous circuits based on timed Petri nets that might help corroborate such claims. Features of our work include the ability to handle circuits with data de-pendent execution times, as well as the consideration of arbitration and resource usages. Performance evaluation of synchronous circuits is al-most always carried out in terms of the clock cycle time. The performance analysis problem is much more difficult for asynchronous circuits as they do not employ a global clock. In addition, the execution of asynchronous circuits is concurrent as well as data- and resource-dependent in nature. We believe that timed Petri nets can model systems with these characteristics. Related Work and Overview or Approach Asynchronous circuit performance analysis has been con-ducted at an analytical level by Sparsoe [19] and Williams ·Supported in part by NSF Award MIP-921S878 1063-6404/94 $4.00 © 1994 IEEE 221 Department of ECE University of California, Davis, CA 95616 [21], who study asynchronous pipelines. Petri Nets have been widely used for studying asynchronous computations [16] as well as for modeling as well as synthesizing syn-chronous and asynchronous circuits. They have also been widely used in performance analysis studies at the system level. Basically one can observe two categories of works in this area. In the first category, decision-free Petri net structures are used to model computations [18] while in the second category. Petri nets with decisions (or "choices'') are allowed [22, 10]. Recent work on asynchronous circuit per-formance analysis falling under the first category include the works of Burns and and Williams [5, 21]. These authors model the computation as a constraint-graph and solve per-formance equations using linear programming techniques. Work by Hulgaard et al. [8] adapt the work by Burns and provide an algorithm to find exact bounds on the time sep-aration of events in a branch-free process graph. Nielson and Kishinevsky [17] address the problem of determining the cycle time and critical paths through timing simulation. These works do not consider data dependent behaviors, arbitration for resources, and/or conditional branches. The main contribution of this paper is to demonstrate that using an existing Generalized Timed Petri Net (G1PN) model [10] (detailed in Section 3), it is possible to hierar-chically model a wide class of asynchronous circuits and systems in a uniform manner. while taking into account arbitration. resource usages, as well as data dependent be-havior. 2 Modeling Self-timed Circuits We assume two-phase transition signaling (up-going and down-going transition of a signal have the same mean-ing) and assume one wire per bit of data with the data-bundling assumption[20]. For concreteness, we assume macromodules-style circuits [20, 3, 2]. Macromodule cir-cuits can be classified as control blocks (CB). datapath ~locks (DB), and data-dependent control modules, or pred-Icate blocks, PB (the latter two are illustrated in Figure 1). Examples of primitive CBs include the XOR gate, the Muller C-ELEMENT, and the CAll module. In Figure I, the delay !ine associated with DB models its worst-case delay. PB Implements data-dependent control flow, e.g., conditional branches. '--.. 1_ .. --" ..,_ .. _- ..... Figure 1: Models for DB andPB A self-timed circuit can be represented by a one-safe Petti net [14, 6] which is obtainable by composing the Petti nets corresponding to various circuit elements. The name of a wire is attached to each Petti-net transition, and the firing of the Petri-net transition represents a signal transition on this wire. Each Petti net has inltial places (IP) and fiNJl places (FP) that are disjoint, and correspond to the input- and output-ports of the circuiL The operation of a self-timed circuit is modeled by placing tokens in IP (corresponds to a reqlll!st) and waiting for tokens to appear in FP (corresponds to an acknowledge). The environment of the circuit is responsible for placing the tokens in IP and removing the tokens from FP. 3 Generalized Timed Petri-net Theory Timed Petri Nets A GTPN (P, T, A, Mo, D, F, R) [10] is a Petti net which has been augmented to include a set of firing durations (D), a set of firing frequencies (F), and a possibly empty set of resources (R) associated with ~h transition, in addition to the usual fields of the set of places P, the set of Transitions T. the flow-relation A ~ ((P x T) U (T x P», and the initial marking Mo. Each transition is associated with a start firing event and an end firing event in between which the firing of the transition is in progess for a deterministic firing duration of D units of time. The removal of tokens from a transition's input places occurs at start firing while the placement of tokens on a transitions's output places occurs at end firing. While the firing of a transition is in progress, the time to endfiring, called the remaining firing time (RFI), decreases from D to zero. Thus, the state of a GTPN includes the distribution of tokens and the RFI' values of currently active transitions. Each transition of a GTPN is generated by a set of start firing or a set of end firing events that occur simultaneously. The maximal set of transitions that can start firing simultaneously defines the next state of a G1PN. The frequencies, F, associated with ea:h transition are used in assigning probabilities to the next state of the Petri net. 222 Modeliq of delay and firin& frequendes The key timing parameter employed in our work is D, the delay of a transition. D can be obtained from a library, through experiments, or through known timing estimation techniques. Additional conventions in delay modeling are now explained. A transition in the Petti net indicating a signal transition at the output of a gale is annotated by the delay of the gate, while a Petti-net transition indicating a signal transition at the input of a gale is annotated by the delay of the wire from the output of the driving gale to this input. For DBs, a transition indicating the acknowledge signal from a DB is annotated by the average case delay of the DB. Transitions indicating acknowledge signals from a PB are annotated by the sum of the average cae delay of logic block associated with the PB and the delay of the Select element used in generating the aclcnowledge transition. Firing frequencies (F) can be assigned to any transition. In case of a place with two or more arcs leading out of it (indicating a choice), branching frequencies may be as-signed based on data dependent branching information. We note that the equivalent circuit paradigm of such an occur-rence in the Petri net is a PB, which is a Select element whose conttol signal behavior is data dependent. All othez transitions are assumed to have a firing frequency of 1. Background on GTPNA analysis We present below a quick overview of the GTPNA anal-ysis techniques from Holliday [10], for the sake of com-pleteness. Some of the relevant tezminology and the0-rems of Markov Chain theory are also presented here. A detailed discussion of the Discrete-TIme Markov Chains and their relationship to stochastic Petti nets are described in [1, IS]. The suonglyconnected components of the state space (when viewed as a directed graph) are the classes of the Markov Chain. The condensed graph (one vertex for ea:h class) is a directed acyclic graph with one rooL In the case of a finite state space, the interior vertices of the con-densed graph are called transient classes. The leaf vertices of the condensed graph are called recll11'ent classes 'R. In a typical evolution of the system being modeled, the system starts in a state in the root of this condensed graph. It then filters through the transient classes until it is absorbed by one of the recurrent classes. Once absorbed it stays in that recurrent class permanently. In a G1PN, we are interested in the long run (or "stealy statej behavior. Once absorbed in a particular recurrent class, the long run probability distribution over the states in the recurrent class needs to be computed. This stationary probability distribution n 1t is easy to find since it is the unique solution to the set of equations n1t = n1tP1t and EiE1l ni = l, wheremattixP1l = {Piili,j E'R}. Here, Pai refezs to the probability of visiting state j from state i where both states are within the recurrent class 'R. The fact that E..t E.1t ITj = 1 ~ds to the fact that the set of states x IS a recll11'ent class, I.e., once execution enters 'R, it does not leave 'R. Both Pij and Pi are obtained from the underlying state graph of the timed Petri net [9]. Equation nR = TInPn corresponds to the fact that in the long run, instead of having a probability of going from state i to state j in the recurrent class 'R (as defined by the transition matrix), we now have a vector of prObability values TIn of visiting each state i in the recurrent class 'R-. Let S be the set of states in recurrent class 'R- and let S1 be a state in S. Also, define RelTime(s1) to be the time spent in state S1 relative to the long-run time for'R. The long-run time for any state S1 in a recurrent class 'R- defined as . ( EkES TimelnState(k) TIk LongRunTlme S1) = TI 'I (1) where TimeInState(k) is the time spent in state k which is determined from the user given timing annotations in the Petri net and ~ is the probability of visiting state i in the long run. Note this notion of long-run time is analagous to the notion of cycle time for the same state if data dependent choice were not present. ReITime(st) is given by . TimelnState(s1) TIsl RelTlme(s1) = EkES TimelnState(k) TIk (2) We also can obtain for each recurrent class, the utiliza-tion of the resources while in that class. The expectation of Resource Usages for a recurrent class, E[Resusages], is given by E[ResUsages] = L ResUsages(k) RelTime(k) (3) kES where ResU sages( k) is the amount of resources used while in state k of the recurrent class. Performance Estimation In estimating the performance of asynchronous circuits, we employ the long-run time, the RelTime in a state and re-source usage as performance measures. Our usage of long-run time in this manner is related to Zuberek's [22] use of this notion on examples with a single recurrence class. It is important to note that long run time is useful in the compar-ison of different designs and serves as a numerical measure with which to compare the designs. For example, Zuberek has suggested that by using this approach two architectures can be compared against each other, although he does this only for systems that can be modeled as Petri Nets with a single recurrence class. The ratio of the performance of an optimized and unoptimized design gives us a fair idea of the amount of improvement we can see in the optimization process. 223 Table 1: Table of experimental results Circuit Numof Perf. (ns) CPU (secs) Name states Long Run Time (GTPN) EXOPT 223 1620 0.25 EX-RF 223 1420 u.25 EX-MVPC 223 1560 0.25 WAVE} 428 1010 0.13 WAVE2 428 1490 0.13 WAVE3 428 212U U.13 ARP 44 0.05 ARP-OPT 44 0.05 4 Results and Conclusions We have been able to analyze reasonably large examples and obtained performance estimates in less than a second of CPU time in most cases as shown in Table 1. First, the ex-ecution unit of the NSR [4] processor was modeled, shown as EXOPT in Table 1. Then, optimizations were performed on this model, and the long run times for a particular state of interest were compared. In the second example, that of a crossbar arbiter [7], the probabilities of connection requests for the crossbar switches was varied and the performance was compared in terms of the long run times, as shown in WAVEl, WAVE2 and WAVE3. Finally, an Asynchronous Reordering Pipeline [12] was also analyzed. ARP is an unoptimized version of this circuit and ARP-OPT an opti-mized version based on data dependent probablities of the reordering requests. These examples are discussed in detail in [11]. Although the GTPN analysis tools are very efficient in generating the reachability graph and use good numerical techniques for analysis, the problem of state explosion in generating the reachability graph of the Petri net can be significant in some cases. This was noticed while trying to analyze another version of the crossbar arbiter called the crisscrossing arbiter [7] which is very decoupled in its execution. This analysis could not be completed even for a 4x4 crossbar switch. Therefore, more efficient techniques to generate the reachability graphs are necessary. Statistical reasoning can, in general, introduce errors in the analysis, because of the fact that the performance of the underlying net is abstractly represented by its long-run time. For the NSR processor's execution unit, we observed that our analysis gave results in close agreement (in the sense of tracking) with the actual chip's measured performance. The exact magnitude of the error will be studied in our future work. Another possible source of inaccuracy in our current approach is the following. In modeling the delay exhibited by data blocks whose computations are data dependent at a fine-grain level (e.g., carry-completion addition), we currently take the average delay exhibited by those units with respect to the distribution of the data being handled by those units. A more direct way to incorporate the data dependent delays of data blocks has to be investigated. Finally. macromodule based circuits lend themselves very well to Petri net based analysis. HOWever. we would also like to consider other classes of asynchronous circuits as part of our future work. References [1] AJMONB MARsAN. O. B •• AND CONTE. O. Perfor-mance Models of Multiprocessor Systems. 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Performance analysis and optimization of asynchronous circuits

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Performance analysis and optimization of asynchronous circuits

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