technical reportTwo fairly intuitive conditions are given that serve to algebraically characterize Seitz's "weak conditions" for self timed circuits. It is shown that these two conditions embody the 12 temporal logic conditions (developed b y Owicki and Malachi) which are intended to express both the weak conditions as well as certain liveness properties that self timed circuits need to satisfy

Purushothaman, S.

Subrahmanyam, P.A.

English

The University of Utah: J. Willard Marriott Digital Library

An Algebraic Formulation of Seitz's Weak Conditions for Self Timed Circuits S.Purushothaman P.A.Subrahmanyam Department of Computer Science University of Utah Salt Lake City, Utah 84112 UTEC-82-066 October 1982 Abstract Two fairly intuitive conditions are given that serve to algebraically characterize Seitz's "weak conditions" for self timed circuits. It is shown that these two conditions embody the 12 temporal logic conditions (developed by Owicki and Malachi) which are intended to express both the weak conditions as well as certain liveness properties that self timed circuits need to satisfy. This research was sponsored by Defense Advanced Research Projects Agency, US Department of Defense, Contract No.MDA903-81-C-0414. 1 1. Introduction The current trends in VLSI design research point to the development of a theory for VLSI circuits quite analogous to the development of theories for program design and programming languages. The need for (and the advantages of) a rigorous basis that supports a broad spectrum of the VLSI design process is by now well recognized and has been widely argued for. A uniform algebraic framework that supports abstract (functional), architectural, and electrical levels of abstraction, and that is, in particular, intended to aid in the mechanical development of designs proceeding from high level specifications, has been introduced in [4]. In recognition of the increasing importance of self timed implementations, we detail in this note an algebraic formulation of Seitz's weak conditions for such circuits. Our prime motivation here is to recast the work on Seitz's conditions based on temporal logic [lJ, so as to maintain the same algebraic framework at all the three levels of the hierarchy mentioned above. A by-product of this effort is that we have a fairly succinct characterization (in terms of two very intuitive and easy to state conditions) of the 12 conditions enumerated by Owicki and Malachi in [lJ. In section 2 we review some basic definitions that are used in section 3 to algebraically formulate the "weak conditions". Finally, in section 4 we show how the temporal logic conditions proposed in [lJ are embodied by the algebraic formulation. 2. A Model for VLSI Circuits. Some Preliminary Definitions We adopt the prevalent notion that an electrical circuit is a network of processing elements I combinatorial modules (henceforth called modules) having a set of input and output ports. The modules perform computations and can communicate with other modules or with the external world through their ports. In this model, the function of a module can be captured by specifying the data values obtained at the output ports as a (mathematical) function of the values provided at the input ports. The functionality of the module (i.e., its behavior over a period of time,) can be captured by stating certain conditions that must hold on the sequence of input-output vectors. We assume that the data on the I I 0 lines is an element of the set D = {a, 1, l} where I :5 ° and 1:5 1. We.also assume that once an input line becomes defined, it retains the same value until all the outputs become defined. This implies that any transition from the value ° to 1 or vice-versa should pass through the value L A function f is a mapping from a domain A to a domain B, i.e. f: A -> B. We further presuppose an partial ordering :5 on the elements of A and B. A function is said to be total if all the elements of A are mapped by the function f to some element of B, otherwise the function is said to be partial. It is useful to define the "natural-extension" of a partial function as being the padded function that evaluates to 1 whenever any of its arguments is 1. That is, a function f is said to be naturally-extended if if 3 aj :ajE(al,oo.,an) and aj =.1 then f(al,oo.,an) = ~. Given a function f: A -> B, we say that it is monotonic if it "preserves" order, l.e. if it satisfies the condition, 2 A set D = {al, ... arJ.c A, is said to be a chain if al :s; a2 :s; .... :s; an. A least upper bound CU) of two elements aI, a2 belonging to a set A, is an element b E A, such that the following condition holds good: al :s; b, a2 :s; band ('v'c):al :s; c, a2 :s; c imply b :s; c. A function f is said to be continuous if f is monotonic and least upper bounds of chains in A are preserved, i.e., if the following condition holds good:' U (f(al), ... ,f(an» = feU (al,···an)) where (al, .... ,an) is an arbitrarily long chain These concepts are standard in recursive function theory (e.g., see [2]). 3. Seitz's Weak Conditions: An Algebraic Formulation In this section we first review Seitz's weak conditions and then formulate them in algebraic terms. The weak conditions proposed by Seitz in [3] are a set of timing constraints on the allowable transitions of values on the data lines that form the inputs/outputs of a module. These constraints need to be preserved under composition of such modules. Intuitively, the weak conditions state that output lines lag behind the input lines and demand that the input lines be held steady until the output lines reach their final states. As figure 3-1 suggests, the value on a data line should go from being undefined Cj) to being defined (lor 0) and go back to being undefined Cj) over a cycle. If we consider the vector consisting of the data values on the input lines over a cycle, it should change from being (1 ... J) to (d, ... d), where d is 0 or 1 and then go back to the vector (1, ... ,1). The output lines must go through the same transitions. For a formal statement of these conditions using primitives in temporal logic the reader is referred to [1]. The conditions as stated in [3] are recapitulated in figure 3-1. We define a cycle to be the time period in which the input lines go from being completely undefined to being defined, and then back to being completely undefined. The first phase of the cycle is the time period in which the input vector goes from being completely undefined to being completely defined and the second phase of the cycle in which the input lines goes back from being completely defined to being completely undefined. The constraints that embody the weak conditions can be broken down into two classes: - Those that characterize the logic of the module. - Those that characterize the module's interface with the environment and that therefore capture the behavior of the input and the output lines. The protocol that is being used (e.g., the request-acknowledge protocol) typically enforces these conditions. Consider a module M defined by: 1. n input ports (il, ... ,in) and 2. m output ports (OI, ... ,Om) where the outputs are related to the inputs of the module through the functions gl, ..... 'gm as follows: 3 ~ All 1 <= ~ ~ c.. Nonet All 1 ~ ,-"" \ ~ C None+ The Seitz's conditions are as follows: (1) Some inputs become defined:5 some outputs become defined (2) All inputs become defined:5 all outputs become defined I / / (3) All outputs become defined:5 some inputs become undefined ~ I I /(6) I I / (4) Some inputs become undefined :5 some outputs become undefined (5) All inputs become undefined :5 all outputs become undefined ( (6) All outputs become undefined :5 some inputs become defined Figure 3-1: Weak Conditions 01 = gl (i1,l, ... ,i1,k1), where (h,l . .i1,k1) .c (il.·.in) ( We define an input vector I for a module Mas <ib .... ,in>, an output vector 0 for a module as <Ol, ... ,Om> and a combined 110 vector C for each module as <il, ... ,in,Ol, .... 'om>' where h to in "are the values on the n input lines to the module and 01 to om are the values on the output lines at any time instance. The weak conditions for a Module M can now be stated as follows: 4 Condl: Given a sequence of I/O vectors Cl, .... ,Ck at k time instances over a cycle, the elements of the sequence must satisfy the following relation, C1 ::S C2 ::S .••• ::S D ~ ..... ~ Ck, where Cl = 1. m + nIl. C = ..Lrn + ~+n ' ~ is the vector (.[.., ... .1.) of m + n elements, D is the vector (d, ... d) of m + n elements, where d is either 1 or 0 and ~ is the inverse of the partial order ::s. Cond2: The functions (gj,i = i .. m) must be total, monotonic and naturally-extended functions. The first condition depends entirely on the environment and the input and output lines, whereas the second condition characterizes the logic of the module. Given two modules which satisfy the two conditions, it can easily be shown that a composition of two modules with no feedback is closed under composition as follows: Proposition 1: The condition Condl is trivially satisfied under composition as, for any chain {Sj} in domain D, and a chain {Rj} in D', the sequence of tuples {<Sj,Ri>} is a chain in the cross product D X D' of the domains D and D'. Proposition 2: As composition of two total monotonic naturally-extended functions is again a total monotonic naturally-extended function [2J, the condition Cond2 is preserved under composition. 4. Sietz's Weak Conditions: A Temporal Logic formulation We now briefly review some relevant definitions in temporal logic, state the formulation of weak conditions proposed in [1] and prove that the conditions Condl and Cond2 stated in the last section are equivalent to the temporal logic formulation of the same. 4.1. Temporal logic Temporal logic is a modal logic, wherein the usual first order propositional calculus is upgraded with modal operators for reasoning about sequences over time. The modal operators used are usually from the set {O, <>, [], U} and when used with propositions, state properties about the future. The usual model used for temporal logic is a sequence of time instances, where the first element of the sequence is the present and subsequent elements are the future. Informally, the semantics of the modal operators are as follows: Op <>p [J P pUq the proposition p will be true in the next instance p will be eventually true p is true now and will remain true in all future time instances either q is true now or p is true now and will remain true until q is true. Stated formally, p U q = q V (p A O(p U q)) Temporal logic can be used to reason about second order properties of parallel programs like termination, liveliness, freedom from deadlock etc. In specifying some of the properties of asynchronous circuits, we will use some derived operators. Their definitions follow: Operator While Definition p W q == p U (- q) Precedes Latched While Entails p P q = (~q) Up pLWq=p~pWq P -> q = P ~ <> q 4.2. Weak conditions in Temporal Logic 5 In this section we will state the weak conditions in temporal logic [1] and argue that the conditions Condl and Cond2 are equivalent to the temporal logic specifications. Throughout this section we will assume that we are given a module M, a set of input lines I, that has a set of output lines 0 together with a set of functions {gi, i = Lm} such that, 01 = gl (il,l, ... ,i1,k1), where (il,1 . .il,k1) .c (il··.in) where 0 = <Oi, i = Lm> and I = <ij, j = Ln> and the concatenated vector C = <iI .. .in,Ol ... Om>. Associated with the lines I and 0, we define a function d, such that d(i) = true if the line i is defined (Le., the value on the line i is either 0 or 1) and false when the value on the line is I. We extend d to a set of lines, by defining d(I) =def (3i £ l).(d(i» and define a function D over a set of lines as D(I) =def ('vi £ I). (d(i» In stating the weak conditions in temporal logic, we will state them in the form, ex ~ [] w abbreviated as ;= w where ex is the set of initial conditions. The initial condition ex in all the temporal specification will be ~d(I) A ~d(O). The initial conditions correspond to a part of our condition Condl. ~d(l) implies that I = l-n, and ~d(O) implies that 0 = ..Lm. As condition Condl states that the vector C is initially 1 m+n, the initial condition holds in our system. In proving that our conditions are equivalent to the weak conditions as stated by Owicki, we need to prove that Proposition 3: Condl A Cond2 ~ 1= ~d(O) LW ~d(l) (81) and. 1= -D(O) LW -Den (82) and 1= D(l) -> D(O) (L2) and 1= D(I) LW -D(O) (E3) and 1= D(O) LW D(I) (84) and 1= d(O) LW d(l) (85) and and and and and and 1= -del) -> -d(O) 1= -d(I) LW d(O) 6 1= [D(I) P -d(l)]::> (Vi E I).[d(i) LW - D(l)] 1= [DCOI P -d(Ol] ::> (V 0 E OUd(o) LW -D(O)] 1= [-d(l) P D(I)] ::> (V i E l).[ -d(i) LW d(l)] 1= [-dCO) P DCO)] ::> (V 0 E 0).[ -dCo) LW d(O)] (L5) (E6) (E7) (88) CE9) (810) We provide proofs for two of the conditions here, as all the others can be proved along similar lines. Prooffor Condition 81 Condition 81 states that Cond1 A Cond2 ::> 1= -d(O) LW -d(l) i.e., Cond1 A Cond2 ::> 1= -d(O) ::> -d(O) W -d(I) (using the definition ofLW) i.e., Cond1 A Cond2 ::> 1= -dCO) ::> -d(O) U d(l) (using definition ofW) If the above were not true, it must the case that 3t : d(O) A -d(I) at time t. Hence, at time t, I = (1-.. J) and gj (l ... J):/;-1, which contradicts the assumption Cond2. -Proof for condition E3 Condition E3 states that Cond1 A Cond2 ::> 1= D(l) LW -DCO) The antecedent of the equation is D(l) LW - DCO), which is equivalent to D(l) ::> D(I) W - DCO), which is equivalent to D(I) ::> D(I) U D(O). If the antecedent (*) is false, then 3t :P A O( - D(I) A - 0(0)) at time t, where P = D(I) A -D(O) which implies that the state vectors at time t-l (Ct-l), t (Ct ) and t+ 1 CCt + 1) are Ct-l = (D(l), -DCO», Ct = (DCI), - DCO», and Ct+l = (-D(I), -DCO» which contradicts assumption Cond1, Hence the condition E3 is true. • To complete the proof we have to prove that the implication in the other direction is also true, -.' : 7 i.e. Proposition 4: 81 to 810 :=J Condl A Cond2 We first provide a prooffor Cond2. Consider an output line op. Without loss of generality we assume that the data value on the line op is a function of only one input line, say ik. Thus we have that op = gp (ik). If the function gp is not monotonic, this implies the existence of time instances j and j + 1 and of input and output vectors Ij, Ij + 1, OJ, OJ + 1, such that, when Ij ::; Ij + 1, either OJ 2:: 9j + 1 or OJ and OJ + 1 are not comparable. Given that we have a domain containing only three elements, OJ 2:: OJ + 1 :=J op at j is 1 or 0 and op at j + 1 is 1, without loss of generality. (**) The statement (**) violates the condition 85. If it is true that Ij ::; Ij + 1 and OJ and OJ + 1 are not comparable, we must have that op at j is 1 and op at j + 1 is 0 or vice-versa. This violates our assumption that the transition between the data values 1 and 0 has to pass through 1. Hence the function gp has to be monotonic, which proves our condition Cond2. Before we proceed with the proof for Condl, we wish to point out that the conditions E7, 88, E9 and 810 do not capture the requirement that the input or output values once defined, remain unmodified until all the other lines also become defined. The new conditions are as follows [5]: -d(I) :J ['v'i E 1. d(i) LW -D(!)] U D(l) -d(l) :=J ['v' 0 E O. d(o) LW -D(O)] U D(O) D(I) :=J ['v'i E 1. -d(i) LW d(I)] U -d(l) D(l) :=J ['v' 0 E O. -d(o) LW d(O)] U -d(O) The proof for Condl now follows: From E3 and 84 we obtain, D(I) :=J D(I) U {D(l) and D(O)} D(O) :=J D(O) U {D(I) and D(O)} (ET) (88') (E9') (810') (E11) (E11') which says that once D(l) is true, it remains to be true until both D(l) and D(O) become true. The same is true for D(O) as well. From ET, we obtain for any input line i, d(i) :=J d(i) U D(l). From E11 and the definition of D(l), we get d(i) = > d(i) U D(I) and D(O) (EI2) Consider a sequence of time instances, such that - d(I) A - d(O) is true in the first instance, and both Dill and D(m are true in the last instance. From E12, it directly follows that the input line i, over this sequence, has values 1, ... 1. d(i), ... d(i) (EI4) Given the assumption that the transition in data values on any input or output line, from 0 to 1 or vice-versa has to pass through the value 1. we can impose the following condition on the sequence of elements in E14 1 :5 ... :5 d(i) :5 d(i) Similarly from S8', we can obtain the condition for an output line 0, as 1 :5 ..... :5 d(o) :5 d(o) Taking the cross product of all input and output lines at all instances, we obtain from E12 and E13, l m+n <: C <: C <: Dm + n - 1 - 2 -... , which is part of our Condl. Similarly from E9' and SID', we obtain the other part of our Cond2, Dm + n > C > C I m + n - k- k+l"'-L ' which proves the proposition 4. • It follows from propositions 3 and 4 that the conjunct of the conditions SI to SID' IS equivalent to Condl and Cond2. • 5. Summary. We have presented two very intuitive (and algebraically simple to state) conditions that capture Seitz's weak conditions characterizing self timed circuits (and the 12 conditions discussed in [1]). In practice, specialized "protocols" for implementing asynchronous communication are designed that are intended to guarantee that the weak conditions are met e.g. the double rail/request-acknowledge protocol. Thus, the average designer does not have to be cognizant of the conditions themselves, but only needs to know one or more protocols that provide "correct" implementations of the conditions. However, the conditions to be obeyed may in general be viewed as "specifications" that any newly proposed protocols must satisfy. Thus, in addition to being intuitive, it is hoped that the algebraic statement of the conditions to be met will facilitate such proofs in the overall framework for design that has been developed in . [4]. 9· References [1] Y. Malachi and S.S.Owicki, Temporal Specifications of Self-Timed Systems, pp. . 203-212, Proceedings of the 1981 CMU Conference on VLSI Systems and Computations, Computer Science Department, Carnegie-Mellon University, (October 1981). [2] Manna, Z, Mathematical Theory of Computation, (McGraw--Hill,1974). [3] Charles Seitz, System Timing in: Mead C. and Conway L., Ed., Introduction to VLSI systems, (Addison-Wesley, Reading MA, 1980), pp. 218-262. [4] Subrahmanyam, P.A., An Algebraic Basis for VLSI Design, Draft of a Research Monograph, Apri11982. Available from the Department of Computer Science, University of Utah. [5] Y oni Malachi, Personal Communication . 

An algebraic formulation of seitz's weak conditions for self timed circuits

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An algebraic formulation of seitz's weak conditions for self timed circuits

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