Limits to precision impose limits to the complexity of analog circuits, hence fuzzy analog
controllers are usually oriented to fast low-power systems with low-medium complexity. This
paper presents a strategy to preserve most of the advantages of an analog implementation, while
allowing a marked increment in system complexity.The works in this papaer has been partially funded by the spanish
C.I.C.Y.T. under contract TIC96-1392-C02-02 (SIVA

A. Rodríguez-Vázquez

Costa

F. Vidal-Verdú

Masetti

Navas

R. Navas-González

Electronics Letters

English

El pdf del artículo es la versión pre-print.Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the advantages of an analogue implementation, while allowing a marked increment in system complexity, is presented.The work in this paper has been partially funded by Spanish CICYT under contract TIC96-1392-C02-02 (SIVA).Peer Reviewe

Vidal Verdú, Fernando

Navas-González, Rafael

Rodríguez-Vázquez, Ángel

Digital.CSIC

Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 0A multiplexing architecture for mixed-signal CMOS fuzzy controllers Limits to precision impose limits to the complexity of analog circuits, hence fuzzy analogcontrollers are usually oriented to fast low-power systems with low-medium complexity. Thispaper presents a strategy to preserve most of the advantages of an analog implementation, whileallowing a marked increment in system complexity. Introduction: Because analog fuzzy controllers operate in fully parallel mode, they are wellsuited for applications that require high operation speed. However, the most complexmonolithic analog controller chips reported to date feature 13-rule at 3-input [1] and 16-ruleat 2-input [2] − much smaller than the up to 100-rule and 4-input reported for digital chips[3]. A major obstacle to increasing the complexity of fully-analog controller chips is theexistence of global computation nodes where the errors caused by the rule antecedentcircuits are aggregated; for instance, the centre of gravity is evaluated in such a node. Thisobstacle is specially pertinent for those architectures based on lattice partitions of theuniverse of discourse because these partitions (otherwise advantageous for controlapplications [4]) make the rule count increase exponentially with the input count. Thus, theaccumulated error increases exponentially as well, and the system architecture may becomeunfeasible even for low numbers of inputs. This paper presents a novel mixed-signal controller chip architecture which maintains thefully-parallel operation feature of analog chips but obtains the accumulated errorindependent of the number of rules. It takes advantage of the fact that each fuzzy ruleinfluences the system output only inside a local, limited region of the universe of discourse.Consequently, the universe of discourse can be split into sub-regions and the output foreach sub-region can be calculated by only evaluating a reduced number of fuzzy rules(called active rules [5]). This number is the same for each sub-region, but the correspondingrule parameters differ from one region to another. Our proposal implements this reducednumber of rules by a low-dimension programmable analog processor, and employsSubmitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 1multiplexing to cover the entire universe of discourse. On chip digital circuits are employedfor multiplexing and for programmability.      Architecture and Functional Description: Consider the bi-dimensional lattice partition inFig.1. It shows the universe of discourse split into interpolation intervals, each having adifferent set of active rules. For instance, any input pair  in the light-shaded interval maps onto an output determined by the rules in thedark shaded interval (active rules) while all remaining rules have no influence on the output.Only the active rule membership functions and their associated singleton values are neededfor the interpolation procedure. In addition, the only membership function pieces neededare those which actually contribute to the system output. Thus, in the case illustrated inFig.1, only the pieces drawn with thick lines and the singletons associated with the fouractive rule consequents,  are needed to generate theoutput in the interval .Fig.2 shows the proposed architecture for a controller with  inputs,  labels per input(thus  rules), and with  bits per singleton. It comprises the following blocks:•A/D Converters: Their function is to encode the interpolation interval  associated withthe current input. There are , one per input, with a resolution equal to the next superiorinteger , i.e. . Thus, this battery of converters provides a word ofbits that drives the interval selector block and the digital memory block. • Interval Selector: It selects a set of voltage values  to drive the analog coreand, thus, makes it implement the active membership functions.•Digital Memory: It selects the active singleton programming values  thatconfigure the rule block of the analog core consequents of the active rules. These are digitalwords of as many bits as needed to encode the required set of singleton values.x1 x2,( )Cij ε1i ε1i 1+,( ) ε2i ε2i 1+,( )×[ ]=yij* yi j 1+( )* y i 1+( )j*   and y i 1+( ) j 1+( )*, ,CijM LLM SCijMlog2L ints log2L( )M ints log2L( )[ ]E1… Ek…EM,y1*… yl*…  , y2M*,Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 2•Analog Core: It performs the fuzzy computation having a set of programming inputs whichare driven by the interval selector and the digital memory blocks. These inputs set up theanalog core to work with the rule set that determines the system output, which means  speci-fying the membership functions associated with the rule antecedents as well as the singletonvalues related to the consequents.The internal architecture of the analog core is the same asfor the fuzzy controller in [2], but just  rules are needed here, and only two membershipfunctions per input. Results and conclusions: An example 64-rule, 2-input, 4-bit singleton controller ( , and ) has been designed in a CMOS 0.7μm technology to demonstrate theviability of the proposed architecture.High-speed flash A/D converters are used for interval encoding. The poly-silicon resistorarray used to generate the converter thresholds is also exploited to generate the intervalselector voltages. Thus, this latter block includes only analog switches and some logic. Thememory block is designed carefully so that the data are put in the singleton programmingbus in the proper order − necessary to reduce the memory size by a factor of . Finally,the 4-rule 2-input processing core is constructed by using building blocks similar to thosepresented in [2].Fig.3 shows the DC surface response of the controller for a case where the singletons arechosen to clearly display all the interpolation points. The DC accuracy was around 1%.Fig.4 illustrates controller transient behavior for different values of  (2.80V, 2.90V, 2.95Vand 3V) forcing  to change for each of these values. The input was chosen so that thetrajectory goes through different sub-regions. The delay time, including the time requiredfor dynamic reconfiguration, is around 500ns. Chip power consumption is 16mW.It is illustrative to compare the speed, area and power of this mixed-signal controller tothat of a pure analog one with the same number of inputs and rules anddigitally-programmable singletons. Assuming that the singletons are encoded with the samenumber of bits, the size of the digital memory is the same for the two controllers. However,2ML 8=M 2= S 4=4x2x1Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 3while the number of rule blocks is  for the fully-analog one, it is only  for the newone. The larger the ratio  the more advantageous and less error-prone is thenew architecture as compared to a fully-analog one. Thus, while the circuit in [2] (designedin a 1μm technology) comprises 16rules with 470ns delay, 8.6mW power consumption and1.6mm2 area, the example controller implements 64rules with almost the same delay, 16mWpower and only 1mm2 area.Fig. 1: Universe of discourse split into interpolation intervalsFig. 2: Proposed architectureFig. 3: DC surface response of the example controllerFig. 4: Controller transient behavior F.Vidal-Verdú. Dto. de Electrónica. U.Málaga. Complejo Tecnológico, 29081-Málaga,SPAIN. FAX: 34 952132782 Phone: 34 952133326 email: vidal@ctima.uma.esR. Navas-González. Dto. de Electrónica. U. Málaga. Complejo Tecnológico, Málaga, SPAINA.Rodríguez-Vázquez. Instituto de Microelectrónica de Sevilla. Avda. Reina Mercedes s/n,41012-Sevilla, SPAIN.Acknowledgement: The works in this papaer has been partially funded by the spanishC.I.C.Y.T. under contract TIC96-1392-C02-02 (SIVA)References1 S. Guo, L. Peters, and H. Surmann, “Design and Application of an Analog Fuzzy Logic Controller”.IEEE Trans. on Fuzzy Systems, Vol. 4, pp. 429-438, November 1996.2 F. Vidal-Verdú, R. Navas and A. Rodríguez-Vázquez, "A 16 Rules@2.5Mflips Mixed-SignalProgrammable Fuzzy Controller CMOS-1μm Chip", Proc. of the ESSCIRC’96, pp. 156-159, Sept.1996. LM 2Mα L 2⁄( )M=Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 43 A. Costa, A. de Gloria, P. Faraboschi, A. Pagni and G. Rizzotto, “Hardware Solutions for FuzzyControl”. Proceedings of the IEEE, Vol. 83, pp. 422-434, March 1995.4 M. Brown and C. Harris, Neuro-Fuzzy Adaptive Modeling and Control. Englewood Cliffs: PrenticeHall 1994.5 M. Masetti, E. Gandolfi, A. Gabrieli and F. Boschetti, "4 Input VLSI Fuzzy Chip Design able to processan Input Data Set every 320ns", Proceedings of the JCIS’95, Wrightsville Beach, North Carolina,USA, October 1995.Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 5y (μA)A/DA/DINTERVALSELECTORDIGITAL(LM x S bits)x1yw(A)E1 EM2Mints(log2L)ints(log2L)ints(log2L)A/DMEMORYANALOG COREINPUT BLOCKS(ANTECEDENTRELATED)RULE BLOCKS(CONSEQUENT RELATED)xkxMEk y1* yl* y2M*X11 X1i+1 X1LX1iX21X2Lx2x1CijE1iE2jε1i ε1i+1ε2jε2j+1X2j+1X2jFigure 1Figure 2Figure 3Figure 4x2 (volts)x1  (volts)x 1 (volts)y (μA)y* (volts)Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 6A/DA/DINTERVALSELECTORDIGITAL(LM x S bits)x1yw(A)E1 EM2Mints(log2L)ints(log2L)ints(log2L)A/DMEMORYANALOG COREINPUT BLOCKS(ANTECEDENTRELATED)RULE BLOCKS(CONSEQUENT RELATED)xkxMEk y1* yl* y2M*X11 X1i+1 X1LX1iX21X2Lx2x1CijE1iE2jε1i ε1i+1ε2jε2j+1X2j+1X2jFigure 1Figure 2Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 7Figure 3234234050100150                               x1  (volts)x2 (volts)y (uA)Submitted to: ELECTRONICS LETTERS Version of: June 17, 1998 10:47 am 8Figure 4y* (volts)x 1 (volts)y (μA)

A multiplexing architecture for mixed-signal CMOS fuzzy controllers

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