This publication describes methods, techniques, and apparatuses that enable a user equipment (UE) to quickly increase or lower the supply voltage and/or the clock frequency to handle changes in load operating conditions of the components of a system on chip (SoC). The UE uses a dynamic voltage and frequency scaling (DVFS) to handle changes in load operating conditions. During the DVFS, an application processor (AP) writes the supply voltage and the clock frequency settings to shared memory between the SoC, the AP, and a microcontroller unit (MCU). The MCU, then, can change the supply voltage using a voltage controller and/or change the clock frequency using a clock controller, which includes multiple phase-locked loops (PLLs). The utilization of a clock controller with multiple PLLs enables the MCU to trigger a switch between preset clock frequencies much faster than when using a clock controller with a single PLL. Further, the MCU can anticipate the load operating conditions of the components of the SoC and can quickly adjust the supply voltage and the clock frequency settings to run the anticipated load, enabling the UE to save power and increase performance