In this paper we present the impact of classical electronics constraints on a
solid-state quantum dot logical qubit architecture. Constraints due to routing
density, bandwidth allocation, signal timing, and thermally aware placement of
classical supporting electronics significantly affect the quantum error
correction circuit's error rate. We analyze one level of a quantum error
correction circuit using nine data qubits in a Bacon-Shor code configured as a
quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit)
is used as the fundamental element. A pessimistic estimate of the error
probability of the quantum circuit is calculated using the total number of
gates and idle time using a provably optimal schedule for the circuit
operations obtained with an integer program methodology. The micro-architecture
analysis provides insight about the different ways the electronics impact the
circuit performance (e.g., extra idle time in the schedule), which can
significantly limit the ultimate performance of any quantum circuit and
therefore is a critical foundation for any future larger scale architecture
analysis.Comment: 10 pages, 7 figures, 3 table