An experimental demonstration of an error free 100Gbit/s optical time division multiplexing (OTDM) broadcast star computer interconnect is presented. A highly scalable novel node design provides rapid inter-channel switching capability on the order of the single channel bit period (1.6 ns

Deng, K.-L.

Glesk, Ivan

Prucnal, P.R.

Runser, R.J.

English

Name not available

100 Gbit/s computer optical interconnect

University of Strathclyde Institutional Repository

Strathprints Institutional RepositoryGlesk, Ivan and Runser, R.J. and Deng, K.-L. and Prucnal, P.R. (2000) 100 Gbit/s computer opticalinterconnect. Acta Physica Slovaca, 50 (2). pp. 229-234. ISSN 0323-0465Strathprints is designed to allow users to access the research output of the University of Strathclyde.Copyright c© and Moral Rights for the papers on this site are retained by the individual authorsand/or other copyright owners. You may not engage in further distribution of the material for anyprofitmaking activities or any commercial gain. You may freely distribute both the url (http://strathprints.strath.ac.uk/) and the content of this paper for research or study, educational, ornot-for-profit purposes without prior permission or charge.Any correspondence concerning this service should be sent to Strathprints administrator:mailto:strathprints@strath.ac.ukhttp://strathprints.strath.ac.uk/acta physica slovaca vol. 50 No. 2, 1 – 8 April 2000100 Gbit/s COMPUTER OPTICAL INTERCONNECTIvan Glesk , Robert J. Runser, Kung-Li Deng, and Paul R. PrucnalDepartment of Electrical Engineering, Princeton University, Princeton, NJ08544Received 23 September 1999, accepted 16 November 1999An experimental demonstration of an error free 100Gbit/s optical time division multiplexing(OTDM) broadcast star computer interconnect is presented. A highly scalable novel nodedesign provides rapid inter-channel switching capability on the order of the single channel bitperiod (1.6 ns).PACS: 42.79.Sz, 42.79.Ta1 IntroductionAlthough lightwave technology is meeting the demand for point-to-point and long-haul transportof digital information, routing packets at the nodes of the network has typically been carried outusing electronically switched backplane routers. The growing capacity on the Internet is plac-ing an ever greater demand on electronic routing technologies. While WDM can support largeaggregate traffic bandwidths, it is difficult to perform routing functions which may involve chal-lenging techniques such as dense wavelength conversion. Additionally, present WDM laser andfilter tuning techniques rely upon slow technologies which increase the channel access latencyand reduce the effective network bandwidth.Recent advances in optical time division multiplexing (OTDM) have proven this technolo-gys capability to handle the switching and routing needs for future. Channel access in OTDMnetworks is achieved by using time slot tuners and all-optical demultiplexers. Timing precisionof less than 1ps is required to tune, multiplex, and demultiplex individual channels within theOTDM frame.The computer interconnect we are constructing is based upon an OTDM broadcast star ar-chitecture. The high-level architecture and node design is shown in Fig. 1. Nodes transmitinformation at a slow data rate,  , by modulating picosecond optical pulses. By using a scalabletime slot tuner, the pulse is appropriately delayed to correspond to the desired destination timeslot. Data pulses from all nodes are multiplexed into a time frame with an aggregate bandwidthof  , where  is the number of nodes in the network. The pulse spacing between adjacentchannels is      or typically less than 10ps to achieve 100+ Gbit/s. Ultrafast all-optical de-multiplexers like the TOAD are used to extract the desired channel from the high capacity OTDM E-mail address: glesk@ee.princeton.edu0323-0465/00 c  Institute of Physics, SAS, Bratislava, Slovakia 12 I Glesk et al.OpticalInputTransRecvrData OUTto NetworkMUXNode Schematic••••••N x NStarClientInterfaceOTDMInterconnectControllerGControllerReceiverDataControlClockControlReceivedData TOADClock Time Slot TunerOTDM Router ArchitectureLine CardInterfaceNetworkTraffic•••I/OI/OData Time Slot TunerData INfrom NetworkMUXNetworkTraffic•••I/OI/OFig. 1. OTDM network and node architectureframe at the node receivers. Nodes can select the received time slot by using a time slot tuner toalign the clock with an incoming time slot within the frame for all-optical demultiplexing.To perform the functionality of a router, addresses are mapped to specific time slots withinthe network. Routing is achieved by sending each bit of the packet in a unique time slot cor-responding to its destination node. All nodes in the network are synchronized by splitting andamplifying the optical output of a single modelocked fiber laser. Packet routing is performedby rapidly changing the state of the time slot tuner to transmit into time slots corresponding todestination addresses on the network. Recently, several experimental demonstrations [1-3] haveshown that OTDM can meet many of the demanding needs of a router and a multiprocessor in-terconnect system which include full connectivity, low latency, and high aggregate throughput,reliability, and scalability. We report the demonstration of a testbed for a bit-interleaved 100- G-bit/s OTDM broadcast star architecture that was previously proposed [4]. Unique to our networkis a highly scalable, novel node design that provides inter-channel switching within the singlechannel bit period (1.6 ns). By combining this hardware with a highly efficient arbitration proto-col [4], near lossless channel allocation with low latency is achievable for high speed switchingapplications such as future all-optical routers.100 Gbit/s Computer Optical Interconnect 3Fig. 2. Experimental OTDM computer interconnect and node architecture2 Experimental Demonstration and ResultsFig. 2 shows the network and novel node architecture experimental setup. The two key opticalcomponents of the node are the recently developed fast tunable delay line (FTDL) [5] and the ter-ahertz optical asymmetric demultiplexer (TOAD) [6]. A controller card residing in a workstationsends electronic NRZ data at the single channel bit rate, B, and control bits to the driver boardspecially designed to control the two FTDLs on the clock and data fibers. The FTDLs consistof cascaded feed-forward Mach-Zehnder fiber delay lattices designed to produce optical copiesof the incoming pulse stream organized into  -bit subcells spaced by  with inter- subcell bitspacing  [5]. The two modulators controlled by the driver board select one of the       time slots into which one of the copies is transmitted. The FTDLs in the node are used to transmitdata into a selected time slot within the OTDM frame and align the clock with a given time slotfor optical demultiplexing. Ultimately, the dimensionality of the network,  , is determined by, the number of stages in the FTDL. The intermediate processing bandwidth,      , ofthe driver controller and the electro-optic modulators is designed to match the repetition rate ofthe picosecond pulsed fiber laser source and is related to the single channel bit rate as       .Pulses are amplified by EDFAs and distributed to the individual nodes by   splitters. Afternode data modulation and time slot selection, the data is multiplexed by precision fiber delaysfeeding an NxN star coupler. The high bandwidth OTDM frame is broadcast to all nodes in thenetwork. Each node can demultiplex any single channel from the frame using an FTDL on theclock and a TOAD.In our experimental testbed, we populated 16    time slots in the OTDM frame byconstructing 2    stage FTDLs. The single channel data rate was chosen to match the OC-12rate (  = 622.08 Mbit/s). The 2-ps pulsed 1550-nm fiber laser repetition rate and intermediate4 I Glesk et al.Fig. 3. 100 Gbit/s multiplexed data OTDM subcell eye diagram on bandwidth limited detector, and demul-tiplexed TOAD output eye diagrams for three channels in subcell. (a) 100 Gbit/s multiplexed data ODTMsubcell eye diagram (b) Demultiplexed TOADF output eye diagrams.electronic processing bandwidth were set to the OC-48 rate (      2.48832 GHz). Thesimple electronic design of the driver board permits the rapid control of the FTDL and provideslow latency, arbitrary channel selection. The driver board was constructed using 4-bit electronicmultiplexers (Vitesse) and simple logic operating at the OC-48 rate. To produce an OTDM framewith an aggregate bit rate of 100 Gbit/s,  = 10 ps was chosen. Each TOAD was designed witha demultiplexing window width of about 10 ps at FWHM and a polarization splitter was used toseparate data from clock at the output.The 100-Gbit/s multiplexing and demultiplexing experimental results are shown in Fig. 3.According to the design of the FTDL, the 16 time slots in our OTDM frame are arranged in 4subcells each containing 4 time slots spaced by 10 ps. Our network demonstration focused onone of the subcells within the frame. Fig. 3a shows the aggregate eye diagram for a subcell withmultiplexed data from 4 nodes with a fixed pattern, 1 - pseudorandom - 1 - 0, on a bandwidthlimited detector (34-GHz photodetector, 50-GHz oscilloscope). Upon demultiplexing by TOADstuned to the individual channels, each is resolved in Fig. 3b (the 4th time slot is omitted as it is0).We constructed two fully functional nodes to measure the bit error rate (BER) and demon-strate the rapid inter-channel switching capability of the network nodes using an arbitration pro-tocol. These experiments were performed using adjacent channels in the same 100-Gbit/s subcell(Channels 0 and 1). Fig. 4a shows a plot of the BER versus the single channel average data inputpower at the TOAD when Chan 0 and Chan 1 were modulated with pseudorandom data. Foraverage data and clock input powers greater than -21 dBm (13 fJ pulse energy) and -8 dBm (250fJ pulse energy) respectively, several hours of error free operation have been achieved. Addition-ally, we have observed that the TOAD can provide gain to the demultiplexed signal. The inset toFig. 4a shows the eye diagram of the data input (upper trace) and demultiplexed output (lower100 Gbit/s Computer Optical Interconnect 5-26 -24 -22 -2010-1310-1110-910-710-510-310-1chan 0chan 1BERInput power (dBm)Input P  ( m)(a)TOAD InputTOAD Output(b)0 5 10 15time (ns)Node #0Node #10 0 01 1 1 1 10 1 01 1 1 0 1Ti s)Fig. 4. BER of channels 0 and 1 against average single channel input power, and demonstration of rapidchannel selection on bandwidth limited analogou detector. (a) BER of channels 0 and 1 against averagesingle channel input power. Inset: TOAD input and output eye diagrams demonstrating gain. Æ - channel 0,+ - channel 1. (b) Demonstration of rapid channel selection.trace) of a TOAD demultiplexing a single channel of pseudorandom data with identical oscillo-scope settings. The demultiplexed output is larger in amplitude than the input by approximately6 dB.The fast inter-channel switching capability of the network was also demonstrated by usinga previously proposed, low latency arbitration protocol [4] and two nodes of the network. Thereceivers of both nodes are fixed to listen to their own time slots. Each node transmits its binaryaddress at the single OC-12 channel rate into its own time slot. If successfully received, each n-ode then transmits its address into the time slot of the other node. Fig. 4b shows a demonstrationof the protocol using two nodes in the network whose time slots are adjacent in the 100-Gbit/ssubcell. The addresses assigned to Node 0 and Node 1 were 0101 and 0111 respectively. Thetraces shown are the demultiplexed TOAD outputs directly from the analog output of the re-ceivers for the two nodes. After each node successfully receives its own address, the FTDLsrapidly reconfigure within a single bit period to transmit into the time slot of the other node.Note that each node now successfully receives the address of the other in its own time slot. TheFTDLs and driver board electronics are capable of tuning to any one of the 16 time slots in thenetwork within 1.6 ns, greatly reducing the hardware latency of the protocol.6 I Glesk et al.3 ConclusionWe have demonstrated a fully connected 100-Gbit/s OTDM network architecture that offers fastswitching among data channels with reliable, error free operation and low latency. Since the ac-tive components of the FTDLs do not scale with the number of nodes [5], simply adding anotherstage,   , (3 dB additional loss per node), scales the interconnect up to 64    nodes with-out taxing the power budget significantly. If OC-24 (  = 1.24416 GHz) is chosen as the singlechannel data rate and 10-GHz      intermediate processing bandwidth electronics are used, an80-Gbit/s interconnect with a rapid inter-channel switching speed of 800 ps is feasible. In sucha 64-processor architecture, coherent crosstalk does not limit the BER performance significantly[7]. Since the demultiplexer [8] and other optical components in the node can be integrated, webelieve this network is practical for future, high-speed multiprocessor interconnect systems.Acknowledgement This work has been supported by DARPA Contract No. F30602-97-2-0316.References[1] R.A. Barry, V.W.S. Chan, K.L. Hall, E.S. Kintzer, J.D. Moores, et al.: IEEE J. Sel. Areas Commun.14 (1996) 999[2] J.K. Lucek, P. Gunning, D.G. Moodie, K. Smith, D. Pitcher: Electron. Lett 33 (1997) 887[3] M. Tsukada, W. De zhong, T. Matsunaga, A. Masaki, T. Oohara: J. Lightwave Technol 14 (1996)1979[4] A.G. Nowatzyk P.R. Prucnal: Proc. 22nd Int. Symp. On Computer Arch., Santa Margherita, Italy(1995)[5] K.-L. Deng, K.I. Kang, I. Glesk, P.R. Prucnal: IEEE Photon. Technol. Lett. 9 (1997) 1496[6] I. Glesk, J. P. Sokoloff, P. R. Prucnal: Electron. Lett. 30 (1994) 339[7] K.-L. Deng, I. Glesk, K.I. Kang, P.R. Prucnal: IEEE Photon. Technol. Lett. 10 (1998) 1039[8] E. Jahn, N. Agrawal, M. Arbert, H.-J. Ehrke, D. Franke, et al.: Electron. Lett. 31 (1995) 1857

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100 Gbit/s computer optical interconnect

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