The further improvement of nanoscale electron devices requires support by numerical simulations within the design process. After a brief description of our SIMBA 2D/3D-device simulator, the results of the simulation of DG-MOSFETs are represented. Starting from a basic structure with a gate length of 30 nm, the model parameters were calibrated on the basis measured values from the literature. Afterwards variations in of gate length, channel thickness and doping, gate oxide parameters and source/drain doping were made in connection with numerical calculation of the device characteristics. Then a DG-MOSFET with a gate length of 15 nm was optimized. The optimized structure shows suppressed short channel behavior and short switching times of about 0.15 ps.

Herrmann, T.

Klix, W.

Müller, L.

Stenzel, R.

Acta Polytechnica

English

CTU Open Journal Systems (Czech Technical University, Prague / České vysoké učení technické v Praze)

Notationp, n hole and electron density (cm3) electrostatic potential (V)NA, ND ionized donor and acceptor density (cm3)s permittivity of semiconductor (AsV1m1)q elementary charge (As)Jp, Jn current densities (Acm2)R, G recombination and generation rate (cm3s1)p, n carrier mobilities (cm2V1cm1)p, n quantum correction potentials (V)p, n band parameters (V)Dp, Dn diffusion coefficients (cm2s1)Tp, Tn carrier temperatures (K)kB Boltzmann constant (eVK1)Sp, Sn energy flux densities (Wcm2)E electric field strength (Vcm1)TL lattice temperature (K)wp, wn energy relaxation times (s)mp, mn carrier effective masses (kg) reduced Planck’s constant (Js)p, n quantum correction coefficientp, n thermal conductivities (WK1cm1)1 IntroductionDouble-Gate (DG) MOSFETs are considered to be apromising candidate for nanoscale CMOS. The InternationalTechnology Roadmap for Semiconductors (2005 Edition)predicts printed gate lengths up to 15 nm for the next tenyears. For these gate lengths conventional MOSFETs are lim-ited due to different short channel effects. On the other handstructures with two gates and an extremely thin body demon-strate better control of the gate region and consequentlysuppression of short channel effects.Numerical device simulation is an important procedurefor the design and optimization of novel semiconductordevices. Some advantages are that the electrical behavioriscalculated before the fabrication process, non-measurableinner-electronic values can be calculated and visualizated,and cost effectiveness due to diagnosis/fault-detection in thetechnological process.2 Simulation modelsQuantum hydrodynamic (QHD) models, which are basedon a quantum fluid dynamic model, offer new ways to under-stand and design quantum sized semiconductor devices. Theadvantage of this model is its macroscopic character, whichenables us obtain description without knowing of quantummechanical details like the initial wave function [1], [2], [3].The classical hydrodynamic (HD) model for semiconduc-tor device simulation can be extended by expressions in thetransport equations and in the energy balance equations.These describe an internal quantum potential in the trans-port equation as well as a quantum heat flux in the energybalance equation. These additional terms in the classicalhydrodynamic model allow us to describe the continuouselectron and hole distribution in a semiconductor device,accumulations of carriers in potential wells and resonanttunneling of carriers, respectively. The standard model foruniversal device simulations is the drift-diffusion (DD) model,which can be derived from the above mentioned model [4].Basic equations of the QHD model are the Poissonequation        s D A( ) ( )q p n N N (1)continuity equations (index p: holes, index n: electrons) 	    Jp q R Gpt		(2) 	    Jn q R Gnt		(3)transport equationsJp p p p p B p p       q p D q p k p T   ( ) ( ) ( ) (4)Jn n n n n B n n       q n D q n k n T   ( ) ( ) ( ) (5)©  Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 35Acta Polytechnica Vol. 46  No. 5/2006Numerical Simulation of NanoscaleDouble-Gate MOSFETsR. Stenzel, L. Müller, T. Herrmann, W. KlixThe further improvement of nanoscale electron devices requires support by numerical simulations within the design process. After a briefdescription of our SIMBA 2D/3D-device simulator, the results of the simulation of DG-MOSFETs are represented. Starting from a basicstructure with a gate length of 30 nm, the model parameters were calibrated on the basis measured values from the literature. Afterwardsvariations in of gate length, channel thickness and doping, gate oxide parameters and source/drain doping were made in connection withnumerical calculation of the device characteristics. Then a DG-MOSFET with a gate length of 15 nm was optimized. The optimizedstructure shows suppressed short channel behavior and short switching times of about 0.15 ps.Keywords: Device simulation, semiconductor devices, double-gate MOSFET.energy balance equations 	  	   S J Ep p Bp LwpB pB p3232321k pT TktpTk T R G		( )( )212qpG R qtp		pwpp ( ) ( )(6) 	  	   S J En n B n LwnB nB n3232321k nT TktnTk T R G		( )( )212qnG R qtn		nwnn ( ) ( )(7)energy flux density equationsS J Jp p p B p p p p     ( )TkqT5232(8)S J Jn n n B n n n n     ( )TkqT5232(9)and equations for the quantum correction potentialppp 2 26 m qpp(10)nnn2 26 m qnn(11)Further approaches are necessary for carrier mobilities,generation and recombination rates, diffusion coefficientsand energy relaxation times, which are almost material de-pendent. Equations (1) to (11) are solved self-consistently forthe variables ( , p, n, Tp, Tn, p, n). If equations (10) and (11)are neglected, i. e., for pn 0, the QHD model can be re-duced to the conventional hydrodynamic (HD) model. Ifthe carrier temperatures are set to lattice temperature andequations (6) to (9) are neglected, the quantum drift diffusion(QDD) model and additionally for pn 0 the conven-tional drift diffusion (DD) model can be obtained. Solutionsof the equations are achieved by a successive algorithm (the socalled Gummel algorithm). For solving the partial differentialequations a box method is used. The resulting non-linearequation systems are solved by the NEWTON-method andthe corresponding linear equation systems by preconditionedgradient methods. All models are implemented fully three--dimensionally in the SIMBA program system [5], [6].3 Basic structure simulation andverificationThe starting point for the simulations is a basic structurerepresented in Fig. 1, as a functionally relevant detail of thereal device. The different parameters are assumed as follows: gate length LG  30 nm, source/drain lengths LS  LD  100 nm, gate-to-source and gate-to-drain distancesLGS  LGD  100 nm, silicon film thickness TSi  20 nm, gate oxide thickness Tox  2 nm, channel doping NA  1×1016 cm3, source/drain doping ND  3×1020 cm3.The simulated output characteristics drain current IDversus drain-to-source voltage VDS are plotted in Fig. 2 for36 ©  Czech Technical University Publishing House http://ctn.cvut.cz/ap/Acta Polytechnica Vol. 46  No. 5/2006Fig. 1: Basic structure of the DG-MOSFET0 0.2 0.4 0.6 0.8 1.0 1.201000200030003200I DA/m[]VDS V[ ]VGS = 0.4 VVGS = 0.6 VVGS = 0.8 VVGS = 1.0 VVGS = 1.2 VFig. 2: Output characteristics of the basic structure0 0.2 0.4 0.6 0.8 1.0 1.2I DA/m[]VGS V[ ]VDS = 0.05 VVDS = 1 VSimulation SIMBA[ ]Experiment 7[ ]0.21051041031021011011021031040Fig. 3: Transfer characteristics – Simulation and experimentdifferent gate-to-source voltages VGS. Verification of the simu-lation results and calibration of the model parameters weredone by comparison with experimental values from [7]. Astructure similar to Fig. 1 with LG  45 nm, Tox  2.5 nm,ND  2×1020 cm3 was simulated and compared with themeasured values. The results represented in Fig. 3 show goodagreement. A further successful verification was done by re-sults from [8].4 Parameter variation andoptimizationTo study the influence of the structure parameters on theelectrical device characteristics, various parameters are modi-fied. Figs. 4 and 5 depict the output and the transfer charac-teristics at different gate lengths. At shorter gate lengths athreshold voltage roll off can be observed as a typical shortchannel effect in the particular pinch-off behavior disappearsfor LG < 30 nm. At the same time, the drain saturation cur-rent increases strongly.Variation results of the silicon film thickness are repre-sented in Fig. 6. Thicker channels lead to larger drain cur-rents, and also to a displacement of the threshold voltagetoward smaller values. Therefore the film thickness should benot greater than 20 nm. Thinner gate oxides result in increas-ing drain currents (Fig. 7) and transconductances, and in abetter pinch-off behavior. Therefore the smallest possibleoxide thickness should be applied.©  Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 37Acta Polytechnica Vol. 46  No. 5/20060 0.2 0.4 0.6 0.8 1.0 1.201000200030004000I DA/m[]VDS V[ ]LG = 90 nmLG = 45 nmLG = 30 nmLG = 15 nmLG = 10 nmVGS = 1 VFig. 4: Output characteristics at different gate lengths00.4 0.8 1.2I DA/m[]VGS V[ ]VDS = 1 VLG = 90 nm0.810510410310210110110210310501040.4LG = 45 nmLG = 30 nmLG = 15 nmLG = 10 nmFig. 5: Transfer characteristics at different gate lengths0 0.2 0.4 0.6 0.8 1.0 1.201000200030004000I DA/m[]VDS V[ ]VGS = 1 VTSi =30 nmTSi =25 nmTSi =20 nmTSi = 15 nmTSi = 10 nmTSi = 5 nmFig. 6: Output characteristics at different channel thickness0 0.2 0.4 0.6 0.8 1.0 1.201000200030004000I DA/m[]VDS V[ ]Tox = 1nmTox =1.5 nmTox =2 nmTox =2.5 nmTox =3 nmVGS = 1 VFig. 7: Output characteristics at different gate oxide thicknessVariation of the channel doping causes a decrease inthe drain current for doping densities greater than 1017 cm3(Fig. 8). The threshold voltage is strongly influenced bydoping changes. For optimization of the structures, channeldoping can be used to adjust the required threshold voltage.The source/drain doping should be high enough to reducethe series resistances, whereas the dopant diffusion into thechannel has to be minimized to prevent short channel effects.In this case rapid thermal annealing processes are an es-sential equirement. Fig. 9 shows the corresponding outputcharacteristics.The knowledge gained from the different variations wasused for the design of an optimized structure. A minimaltechnologically practicable gate length of LG  15 nm and agate oxide thickness of Tox  1.5 nm are specified. Furtherobjectives are threshold voltage of VTh  0.1 V, large drainsaturation current and improved dynamical behavior. Afterseveral iterations the further parameters are determined asfollows: TSi  3 nm, NA  2.8×1019 cm3, ND  7×1020 cm3.The resulting output characteristics are represented inFig. 10. Fig. 11 compares the transfer characteristic of theoptimized and basic structure. An enlarged drain current aswell as an improved transconductance can be observed.To determine the dynamical behavior, the gate-to-sourcevoltage was switched from 0 V to 1 V to find the turn-on time(tON) and from 1 V to 0 V to find the turn-off time (tOFF).38 ©  Czech Technical University Publishing House http://ctn.cvut.cz/ap/Acta Polytechnica Vol. 46  No. 5/20060 0.2 0.4 0.6 0.8 1.0 1.201000200030004000I DA/m[]VDS V[ ]NA =1×10cm173VGS = 1.0 VNA =1×10cm16 3NA =1×10cm183NA =5×10cm183NA = 1×10 cm19 3Fig. 8: Output characteristics at different channel doping0 0.2 0.4 0.6 0.8 1.0 1.201000200030004000I DA/m[]VDS V[ ]ND =1×10cm213VGS = 1 VND =1×10cm203ND = 1×10 cm20 3ND = 1×10 cm20 3ND = 1×10 cm20 3Fig. 9: Output characteristics at different source/drain doping0 0.2 0.4 0.6 0.8 1.0 1.20100020002600I DA/m[]VDS V[ ]VGS = 0.4 VVGS = 0.6 VVGS = 0.8 VVGS = 1.0 VVGS = 1.2 VFig. 10: Output characteristics of the optimized structure00.20.40.60.811.2I DA/m[]VGS V[ ]Optimized structureVDS = 1 VBasic structure10510410310210110110210301040.40.20.60.81Fig. 11: Transfer characteristics of the basic and the optimizedstructureFig. 12 shows the time response of the drain current. Thisprovides the switching time of tON  tOFF  0.15 ps. Com-pared with the basic structure the switching times are reducedby a factor of 0.6, primarily due to the structure reduction.5 ConclusionThe scaling down of planar bulk MOSFETs accordingthe International Technology Roadmap for Semiconductorsrequires new structures such as multiple-gate MOSFETs Apromising way to this is with the use of double-gate transis-tors. The implementation will be challenging, with numerousnew and difficult issues. In this case numerical device simula-tion is essential. Variations of different structure parametershave been carried out to calculate the influence on devicecharacteristics. Based on these results an optimized structurewith a gate length of 15 nm was created. The optimized struc-ture shows suppressed short channel effects and switchingtimes of about 0.15 ps.References[1] Gardner, C. L.: The Quantum Hydrodynamic Modelfor Semiconductor Devices. SIAM J. Appl. Math., Vol. 54(1994), No. 2, p. 409–427.[2] Chen, Z.: A Finite Element Method for the QuantumHydrodynamic Model for Semiconductor Devices.Comput. Math. Appl., Vol. 31(1996), p. 17–26.[3] Wettstein, A., Schenk, A., Fichtner, W.: Quantum DeviceSimulation with the Density-Gradient Model on Un-structured Grids. IEEE Trans. Electron Devices, Vol. 48(2001), No. 2, p. 279–284.[4] Selberherr, S.: Analysis and Simulation of Semiconductor De-vices. Berlin, Germany, Springer-Verlag 1984.[5] Klix, W., Stenzel, R.: SIMBA-User Manualhttp://www.htw-dresden.de/~klix/simba/welcome.html.[6] Höntschel, J., Stenzel, R., Klix, W.: Simulation ofQuantum Transport in Monolithic ICs Based onIn0.53Ga0.47As-In0.52Al0.48As RTDs and HEMTswith a Quantum Hydrodynamic Transport Model.IEEE Trans. on Electron Devices, Vol. 51 (2004), No. 5,p. 684-692.[7] Lee, J. H., et al.: Super Self-Aligned Double-Gate(SSDG) MOSFETs Utilizing Oxidation Rate Differenceand Selective Epitaxy. IEDM, Tech. Digest, (1999),p. 3.5.1–3.5.4[8] Vinet, M., et al.: Bonded Planar Double-Metal-GateNMOS Transistor Down to 10 nm. IEEE Electron DeviceLetters, Vol. 26 (2005), p. 317–319Prof. Dr. -Ing. habil Roland Stenzele-mail: stenzel@et.htw-dresden.deLeif MüllerTom HerrmannProf. Dr. -Ing. habil Wilfried KlixDepartment of Electrical EngineeringUniversity of Applied Sciences DresdenFriedrich-List-Platz 1D-01069 Dresden, Germany©  Czech Technical University Publishing House http://ctn.cvut.cz/ap/ 39Acta Polytechnica Vol. 46  No. 5/20060.001 0.01 0.1 1.0 1020102010I DA/m[]t ps[ ]VDS = 1 V0OFF ( = 1 V 0 V)VGS ON ( = 0 V 1 V)VGS Fig. 12: Switching behavior of the optimized structure

Numerical Simulation of Nanoscale Double-Gate MOSFETs

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