Ishibashi, K.

Kawata, Y.

Mizuta, Hiroshi

Oda, S.

Tsuchiya, Yoshishige

Yamaguchi, T.

English

Southampton (e-Prints Soton)

 Observation of Quantum level spectrum for Silicon Double Single-Electron Transistors  Y. Kawata1,2,5, T. Yamaguchi２, K. Ishibashi2, Y. Tsuchiya1,3,5, S. Oda1,5, and H. Mizuta3,4,5  1QNERC, Tokyo Institute of Technology, 2-12-1, O-okayama, Meguro-ku, Tokyo 152-8552, Japan Phone: +81-5734-3854 FAX: +81-5734-2542 e-mail: kawata@neo.pe.titech.ac.jp 2Advanced Device Laboratory, The Institute of Physical and Chemical Reserch (RIKEN), Saitama, Japan 3School of Electronics and Computer Science, University of Southampton, Southampton, UK 4Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan, 5SORST-JST  1.  Introduction Double quantum dots (DQDs) have been studied as attractive candidates for charge qubits. Ini-tially, GaAs-based DQDs formed by means of sur-face gates depletion were studied because many pa-rameters are tunable after their fabrications [1]. However, silicon-based DQDs are more promising for charge qubits because of the absence of piezo-electric electron-phonon coupling, and the effect of phonon localization [2]. Furthermore, to integrate Si multiple charge qubits and a readout device in a small footprint, a series-connected double dots transistor has recently been proposed and studied [3]. The readout is called as double single-electron transistors (DSETs) and facilitates to detect the single-charge polarizations on the adjacent double qubits efficiently [4].  The other advantage of DSETs is that both two SETs act as feedback transistors to each other to compensate the random fluctuation noise.   It is also important to clarify the quantum effects in the vicinity of the charge triple points from a standpoint of future down-scaling of the DSETs and qubits. However, the impacts of quantization on sin-gle-electron tunneling characteristics have not been studied for lithographically-defined silicon DQDs. In this paper, we report on the tunnel spectroscopy of quantum levels on lithographically-defined silicon DSETs at milli Kelvin temperatures for the first time.  2.  Fabrication  of  DSETs The DSETs were fabricated on the SOI substrate with the SOI thickness of 40 nm and the phosphorous doping concentration of 1019 cm-3. An SEM image of the fabricated DSETs with control gates (G3-G7) for qubits (to be integrated) and the equivalent circuit of DSETs are shown in Fig. 1(a) and Fig. 1(b), respec-tively. After lithography and etching to pattern the DSETs, thermal oxidation was done at 1000 °C to passivate the surface states and to reduce the thick-ness of the SOI down to 30 nm. This results in an overall core dot diameter of approximately 55 nm. In this device structure, the adjacent constrictions act as tunnel barriers connecting the dots to the source and drain electrodes.    3. Electrical characteristics for DSETs     Electrical measurements were carried out at the dilution base temperature of 22 mK and the effective electron temperature of around 0.2 K. Figs. 2 (a) and 2 (b) show the contour plot of ID measured and simu-lated respectively as a function of VG1 and VG2 at VDSeff=-7.5 mV, where VDSeff is the voltage drop be-tween the leftmost and the rightmost barriers. The simulation reproduces the measured characteristic because the dots are well defined. From this meas-urement characteristic, the total capacitances of Dot 1 and Dot 2 and the inter-dot capacitance were ex-tracted to be CC1=16 aF and CC2=12 aF, and CCm =3.1 aF, respectively. The corresponding charging energies are  EC1=10 meV, EC2=14 meV, and ECm=2.7 meV. Additionally, gate capacitances CG1D1=0.75 aF, CG1D2=0.50 aF, CG2D2=0.80 aF, and CG2D1=0.70 aF were also extracted from the characteristics. Similar stability characteristics were observed at 4.2 K, and the extracted gate capacitances of the dots were al-most the same as those extracted at dilution tempera-ture of 22 mK. With this consistency in the device characteristics at different temperatures, the origin of the dots is attributed to the well-defined lateral con-finements.   A fine sweep across the charge triple points is shown in Fig. 3 (a). In this measurement, a primary sweep was done with the gate G1. This gray scale plot displays the values of differential conductance (∂IDS/∂VG1) as a function of VG1 and VG2 for VDSeff = -8.5 mV. Fig. 3 (b) blows up the square region marked in Fig. 3 (a) and ID-VG1 characteristics along the dotted line in the (∂IDS/∂VG1) plot. The current peaks in ID-VG1 plot are located between differential conductance peaks in the triangle-shaped region in (∂ID/∂VG1) plot. These current peaks and (∂ID/∂VG1) peaks are caused by the resonant tunneling through DQDs. These high (∂ID/∂VG1) peaks can be used to detect single-charge polarizations for double qubits integrated in the future. Given that all the level inter-vals are the same for two dots, the energy spacing was estimated to be 0.5 meV. This value is in good agreement with the value of 0.6 meV estimated from the dot diameter of 55 nm. Inelastic tunneling rate between the dots Γi. is also estimated to be 3.0×106 Hz at most from the off-resonance current Ioff ≈ 0.48 pA at VG1=0.835 V along the dotted line in Fig. 3 (b). Because of the present device geometry (Fig. 1(a)), the inter-dot tunneling rate at resonance ΓLR is con-sidered to be smaller than ΓL and ΓR, and is dominant where ΓLR ≈3.6×106 Hz can be estimated from the resonant current 0.58 pA at VG1=0.843 V along the dotted line in Fig. 3 (b). Finally, the peak-to-valley current ratio is evaluated to be 1.2.  3. Conclusions    Ｗe observed the spectrum of quantum levels for silicon DSETs, which is composed of DQDs. The quantum dots were attributed to the well-defined lat-References  eral confinement even at the dilution base tempera-ture of 22 mK. The estimated level spacing in quan-tum dots from the characteristics was also in agree-ment with the value from the quantum dot size. The inelastic tunneling rate between dots was quite small compared with GaAs-based DQDs. The observed differential conductance peaks can be used to detect double qubit integrated in the future. [1]  T.  Fujisawa  et al., Physica E 21, 1046 (2004).   [2]  J.  Gorman  et al., Phys. Rev. Lett., 95, 090502 (2005). [3]  Y.  Kawata  et al., SNW 2007, pp.119 (2007). [4]  Y. Kawata et al., SSDM 2007, pp.1126 (2007).    ( a )                            ( b )                                 Fig. 1 (a) SEM image of DSETs and qubits gates (G3-G7). The dotted circles indicate the DQDs integrated in the future. (b) The equivalent circuit of DSETs.  (a)                 (b)                    Fig. 2 Contour plot of ID (a) measured and (b) simulated as a func-tion of VG1 and VG2 at VDSeff =-7.5 mV at dilution base temperature of 22 mK. (a)  ∂ID    ∂VG1   (×10-10)               ID (pA)    ∂ID   (b)                        ２          Fig.3 (a) Contour plot of differential conductance (∂IDS/∂VG1) as a function of VG1 and VG2 at VDSeff = -8.5 mV. (b) The square region marked in Fig. 3 (a) and ID-VG1 characteristics along the dotted line in the (∂IDS/∂VG1) plot are shown. ID (arb. unit) ∂VG1   (×10-10) 

Observation of quantum level spectrum for silicon double single-electron transistors

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