Timing driven genetic placement

Abstract

IN this paper we present a timing driven placer for standard cell IC design. The placement algorithm follows the genetic paradigm, with the objective of minimizing both area and path slacks. At early generations, the search is biased toward solutions with superior timing characteristics. As the algorithm starts converging towards generations with acceptable delay properties, the objective is dynamically adjusted toward optimizing area and routability. Experiments with benchmark test demonstrate delay performance improvement by up to 20%. It is also shown that sizeable reduction in runtime is obtained when population size is allowed to decrease in a controlled manner whenever the search his a plateau. This reduction in runtime is achieved without any noticeable loss in solution quality