We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuristics are based on Genetic Algorithms (GA's) and Tabu Search (TS)[1] respectively. We address a multiobjective version of the problem in which, power dissipation, timing performance, and interconnect wire lenghth are optimized while layout width is taken as a constraint. Fuzzy rules are incorporated in order to design a multi-objective cost function that integrates the cost of three objectives in a single overall cost value. A series of experiments is performed to study the effect of important algorithmic parameters of GA and TS. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compared
