Current placement systems attempt to optimize several objectives, namely area, connection lenght, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propogation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of criticality. Experiments with test circuits demonstrate delay performance improvement by upto 20
