Full-duplex is a communications engineering scheme that allows a single device to transmit and receive at the same time, using the same frequency for both tasks. Compared to traditionally used half-duplex, where the transmission and reception is divided temporally or spectrally, the spectral efficiency may theoretically be doubled in full-duplex operation. However, the technology suffers from a profound problem, namely the self-interference (SI) signal, which is the name given to the signal a node transmits and simultaneously also receives. Making the full-duplex technology feasible demands that the SI signal is mitigated with SI cancellers. Such cancellers reconstruct an estimate of the SI signal and subtract the estimate from the received signal, thus suppressing the SI. For the SI signal to be diminished as much as possible, canceller solutions should be deployed in both analog and digital domains. This thesis presents a digital real-time implementation of a novel nonlinear self-interference canceller, based on splines interpolation. This canceller utilizes a Hammerstein model to identify the SI signal, taking advantage of a FIR filter for the identification of the SI channel, and splines interpolation to model the nonlinear effects of the transceiver circuitry. The new canceller solution promises great reduction in computational complexity compared to traditional algorithms with little to no sacrifice in cancellation performance.
The algorithm was implemented for a National Instruments USRP SDR device using LabVIEW Communications System Design Suite 2.0. The LabVIEW program provides the required connectivity to the USRP platform, as the SDR lacks a user interface. In addition, the functionality of the SDR is determined in LabVIEW, by creating code that is then run on the USRP, or more specifically, on the built-in FPGA of the device. The FPGA is where the SI canceller is executed, in order to ensure real-time operation. Even though the USRP device employs a high-end FPGA with plenty of resources, the canceller implementation needs to be simplified nonetheless, for example by approximating magnitudes of complex values and by decreasing the sample rate of the canceller. With the simplifications, the implementation utilizes only 34.9 % of available slices on the FPGA and only 34.6 % of the DSP units. Measurements with the canceller show that it is capable of SI cancellation of up to 48 dB, which is on par with state-of-the-art real-time SI cancellations in literature. Furthermore, it was demonstrated that the canceller is capable of bidirectional communication in various circumstances
