The complexity of designing SoCs is rapidly increasing and the development of software has a major impact on the overall design cost. Traditionally, the software development could only start after the hardware was complete. Prototyping has brought a left-shift to the software development flow. Prototypes are models of the hardware and they can be developed in different abstraction levels. With high abstraction level prototypes application development can start in parallel with the hardware design. As the project goes further, more accurate prototypes can be made and the software development can move down to be more hardware centric.
When both hardware and software design are finished, integration testing between them needs to be done. For this, a hardware accurate prototype is needed to ensure the correct operation with the final silicon implementation. This HW/SW integration testing can be done with FPGA prototypes. The final Register Transfer Level (RTL) description is synthesized to the FPGA fabric and it is connected to a processor so the software can access the hardware under test. By using an SoC FPGA that has a processor and the FPGA in the same chip, the physical connection between the processor and the FPGA is already available, reducing the development effort required.
In this thesis an SoC FPGA evaluation kit is used to build a test bench for integration testing for a project that has its RTL design complete. In the test bench, two hardware Designs Under Test (DUT) are connected to each other and additional testing blocks are connected to them: a test pattern generator, an error generator and data capture logic. The DUTs were controlled with the software drivers under test and the correctness of test data through the DUTs was observed. The test bench proved to be a viable option for integration testing. Running test cases was fast with the test bench and the test bench was built in short time , allowing an early start of integration testing after the RTL is released
