There have been various theoretical and experimental studies presented in the literature that focus on interfacing neurons with discrete electronic devices such as transistors. It has also been demonstrated experimentally that neural-electronic devices can be used to elicit action potentials in a target neuron in close proximity to the neural-electronic stimulator. The time delay between stimulus and the onset of the neural action potential can be varied by varying the pulse amplitude and width generated by the neural-electronic stimulator (transistor)

Jenkins, Frank

Szlavik, Robert B.

English

DigitalCommons@CalPoly

                                                                                                                                                                                                                                   ____________________________________________________________                                                                                                                                                                                                                                                                                                                                                                                                                                     ____________________________________________________________         Varying the Time Delay of an Action Potential Elicited with a Neural-Electronic Stimulator  Robert B. Szlavik, Frank Jenkins Center for Biomedical Engineering and Rehabilitation Science, Louisiana Tech University, USA Abstract - There have been various theoretical and experimental studies presented in the literature that focus oninterfacing neurons with discrete electronic devices such astransistors.  It has also been demonstrated experimentally that neural-electronic devices can be used to elicit action potentialsin a target neuron in close proximity to the neural-electronicstimulator.  The time delay between stimulus and the onset ofthe neural action potential can be varied by varying the pulseamplitude and width generated by the neural-electronic stimulator (transistor). Keywords – Neural-electronics, neural engineering  I. INTRODUCTIONIt has been demonstrated experimentally by Weis andFromherz, as well as Vassanelli and Fromherz, that a detectable signal can be conducted from a neuron in vitro to a silicon transistor [1] [2]. Nerve cell excitation using a semiconductor based electronic device has beendemonstrated by Fromherz and Stett [3].   Direct interface and subsequent signal conduction between individualneurons and single transistors would, if practically achievable in an in vivo environment, have the potential ofproviding a solution to many of the localization issues associated with conventional non-specific field based functional electrical stimulation (FES) techniques. In motor nerve stimulation applications, it is desirableto recruit different populations of motor units at differenttimes.  A temporally staggered recruitment of motor units would help to mitigate rapid fatigue of the musculature observed in many FES regimes.  The ability to easily varythe time delay between the stimulus and the onset of the action potential could be utilized in motor nerve stimulationapplications where it is desirable to vary the recruitment time of different motor nerve fibers in the nerve trunk and consequently motor units. It is demonstrated in this studythat the relatively simple approach of modulating the neural-electronic stimulator (transistor) drain potential pulse amplitude could be used to vary the time delay between the stimulus onset and the peak of the action potential.  Since ithas been demonstrated through simulation studies thatstimulus pulse width is expected to change the recruitment profile of nerve fibers [4], the impact of variations in the transistor drain potential pulse width is also investigated. II. METHODOLOGYThe modeling approach adopted in this study isanalogous to the approach taken in Szlavik [5].  The physical parameters related to the membrane and the transistor are shown in Table 1., along with the definition of the circuit components. TABLE I LIST OF THE VARIABLES AND PHYSICAL AS WELL AS GEOMETRIC PARAMETERS THAT WERE USED IN THE EQUIVALENT CIRCUIT MODEL aj Interface and nerve cell radius 10 (µm) dj Nerve cell transistor seal distance 10 (nm)L Length of the nerve cell 40 (µm) AΨ Free membrane region area πaJ2 + 2πaJL (cm2) AΡ Interfaced membrane region area πaJ2 (cm2) T Temperature 6.3 (°C) ρJ Extracellular environment resistivity 15 (kΩcm)cJG Gate oxide capacitance per unit area 0.3 (µF/cm2)cNao Extracellular sodium ion concentration 0.491 (mol/L)cNai Intracellular sodium ion concentration 0.05 (mol/L)cKo Extracellular potassium ion concentration 0.02011 (mol/L)cKi Intracellular potassium ion concentration 0.400 (mol/L)GNaM Maximum sodium conductance per unit area 0.120 (S/cm2) GKM Maximum potassium conductance per unit area 0.036(S/cm2) m Hodgkin Huxley first order kinetic variable[6]h Hodgkin Huxley first order kinetic variable[6]n Hodgkin Huxley first order kinetic variable[6]ΨNa Free membrane region sodium conductance (S)ΨK Free membrane region potassium conductance (S)ΡNa Interfaced membrane region sodium conductance (S)ΡK Interfaced membrane region potassium conductance (S) RJ Interface junction seal resistance [1] ρJ / (5πdJ) (Ω) cM Membrane capacitance per unit area 4.0 (µF/cm2) CΨ Free membrane region capacitance (F) CΡ Interfaced membrane region capacitance (F) CJG Gate oxide capacitance cJGπaj2 (F)VNa Sodium ionic (Nernst) potential (V)VK Potassium ionic (Nernst) potential (V)vI Intracellular potential (V)vJ Interface junction potential (V)vM Interface region transmembrane potential (V) vD Drain Potential (V) RD Drain Resistance 1.0(kΩ) Vto Transistor turn on potential 1.5 (V)K Transistor K parameter 1.0 (mA/V2) VDD Transistor drain DC bias 10 (V)                                                                                               Fig. 1.  Non-linear equivalent circuit model of the neural-electronic stimulator.  The equivalent circuit component values are calculated using the physical parameters and formulas shown in Table 1.The non-linear equivalent circuit that incorporates the non-linear properties of the membrane is shown in Fig. 1.This model was developed by dividing the membrane into a region that is interfaced with the electronic device,represented by the Ρ labeled circuit components, and a freeregion of the membrane, represented by the Ψ labeled circuit components [1;7] as per (1). Ψ = A GM m3hNa Ψ Na M 4ΨK = AΨGK n (1)  Ρ = A GM m3hNa Ρ Na ΡK = AΡGKM n4 Fig 1. illustrates that the overall simulation circuit is divided into two parts consisting of an equivalent circuitthat models the transistor and a lumped parameter equivalent circuit model of the neuron.  Consistent with this modeling approach is the assumption that the specificneuron used can be considered a small cell [6]. The coupled ordinary differential equations (2), (3) and(4), were written in terms of the intracellular potential vI, the transmembrane potential vM across the region of the membrane interfaced with the transistor gate vM = vI - vJ, and the drain potential vD. vD VDD dvD dvM dvI (2) − + i + CJG + C − C = 0D JG JGRD RD dt dt dt dv dv dv v vI m D I MC − C − C + − +JG JG JGdt dt dt RJ RJ (3) dvΡ V − Ρ v + Ρ V − Ρ v − C M = 0Na Na Na M K K K M Ρ dt dvIΨ v −Ψ V +Ψ v −Ψ V + C +Na I Na Na K I K K Ψ dt (4)dvΡ v −Ρ V + Ρ v −Ρ V + C M = 0Na M Na Na K M K K Ρ dt The transistor used in the simulation study was assumed to be an insulated gate field effect n-channel enhancement mode device with parameters as shown in Table 1.  Since the device is assumed to be operated exclusively in the active region, the drain current is governed by (5). i = K (v −V )2 (5) D GS to An inverted transistor gate stimulus pulse vS was usedwhere the DC bias value was adjusted to vary the height ofthe non-inverted pulse that occurs at the transistor drain when the gate to source voltage and consequently the drain current was turned off (ie. vGS = 0 V). The DC bias on the transistor drain did not impact the neuron because of the blocking capacitance CJG associated with the insulated gateof the transistor.  Due to the DC bias, the topology andstimulation regime investigated is not optimal from the perspective of power consumption related issues. A multistep ordinary differential equation solver for stiff problems was used to solve the initial value problem associated with the non-linear system of ordinarydifferential equations. III. RESULTSThe impact of the stimulus pulse amplitude at the drainof the transistor on the time delay between the onset of the stimulus and the peak of the intracellular action potential was investigated.  The effect of variations in the stimuluspulse width was also investigated.  Fig 2. illustrates the impact on variation in drain pulse amplitude on the timecourse of the intracellular action potential.  The graph ofFig. 3 illustrates the effects of variations in both stimulusdrain pulse amplitude as well as pulse width on the actionpotential delay time.   Simulation results illustrate that there is a decreased indelay time associated with an increase in the stimulus pulse amplitude.  This can be seen from Fig. 2, where the time course of the action potentials is shown.                                                                        Delay Time(ms) Intracellular Potential (mV) REFERENCEST im e  (m s )  -8 0 -6 0 -4 0 -2 0 0 2 0  4 0  6 0  D ra in P u ls e A m p litu d e  =  3 .6 1  V  D ra in P u ls e A m p litu d e  =  3 .8 0  V  D ra in  P u ls e  A m p litu d e  = 4 .0  V  Fig. 2.  Graph showing the intracellular actionpotentials for different values of drain pulse amplitude. The stimulus pulse with was 200 µs.0  5  1 0  1 5  2 0  2 5  [1]  [2] [3] [4][5] [6] [7]  Weis, R. and Fromherz, P., "Frequency dependent signal transferin neuron transistors," Physical Review E, vol. 55, no. 1, pp. 877­889, Jan.1997.Vassanelli, S. and Fromherz, P., "Transistor records of excitable neurons from rat brain," Applied Physics A, vol. 66 pp. 459-463,1998.Fromherz, P. and Stett, A., "Silicon-neuron junction:  capacitive stimulation of an individual neuron on a silicon chip,"  PhysicalReview Letters, vol. 75, no. 8, pp. 1670-1673, 1995.Szlavik, R. B. and de Bruin, H., "The effect of stimulus current pulse width on nerve fiber size recruitment patterns," MedicalEngineering & Physics, vol. 21 pp. 507-515, Sept.1999.Szlavik, R. B., "Strategies for improving neural signal detection using a neural-electronic interface," IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol. 11, no. 1, pp. 1-8,Mar.2003.Weiss, T. F., Cellular Biophysics Cambridge: MIT Press, 1996.Fromherz, P., "Extracellular recording with transistors and the distribution of ionic conductances in a cell membrane," Eur Biophys J, vol. 28 pp. 254-258, 1999.6 5 4 3 2 1 3 .4  D ra in  P u ls e  A m p litu d e  (V )  3 .6  3 .8  4 .0  4 .2  4 .4  4 .6  S tim u lu s P u lse  W id th  =  2 0 0  µ s S tim u lu s P u lse  W id th  =  2 1 0  µ s S tim u lu s P u lse  W id th  =  2 2 0  µ s Fig. 3.  Graph showing delay time between stimulusonset and the peak of the intracellular action potential as a function of the drain pulse amplitude.IV. DISCUSSIONThe simulations demonstrate that a decrease in the stimulus pulse amplitude as well as stimulus pulse width can result in a three fold increase in the time delay between the initiation of the stimulus pulse and the onset of the intracellular action potential peak.  The impact of stimulusamplitude variation observed with our model is consistent with other studies presented in the literature that utilize alternate models of the neural-electronic stimulator [3]. 

Varying the Time Delay of an Action Potential Elicited with a Neural-Electronic Stimulator

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Varying the Time Delay of an Action Potential Elicited with a Neural-Electronic Stimulator

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