The paper presents a general test calculation principle which serves for producing tests for a wide range of possible faults:  stuck-at-constant logic  level  (single,  multiple), bridging (single), as well as behavioural (functional. single) faults.  The proposed method handles multi-valued logic,  where the number of logic  values is  unlimited.  The level  of circuit modelling is also allowed to vary in a wide range: switch level. gate level, functional level,  
etc. are equally allowed, Both combinational and sequential circuits are considered, The principle is comparatively simple. and it yields an opportunity to be realized by an efficient computer program

Sziray, J.

English

Periodica Polytechnica (Budapest University of Technology and Economics)

PERIODICA POLYTECHNICA SER. EL. E-'G. \·OL. 41. -'0.4. PP. 251-257 (199,) A COMPREHENSIVE METHOD FOR THE TEST CALCULATION OF COMPLEX DIGITAL CIRCUITS .16zsef SZIRAY Szechenyi College Faculty of Informatics and Electronic Engineering Hedervari ut 3. H-9026 Gyor. Hungary E-mail: sziraygrsl.szif.hu Received: .J une .s. 1997 Abstract The paper presents a general test calculation principle which serves for producing tests for a wide range of possible faults: stuck-at-constant logic level (single, multiple), bridging (single), as well as behavioural (functional. single) faults. The proposed method handles multi-valued logic, where the number of logic values is unlimited. The level of circuit modelling is also allowed to vary in a wide range: switch level. gate le\'el. functional level. etc. are equally allowed, Both combinational and sequential circuits are considered, The principle is comparatively simple. and it yields an opportunity to be realized by an efficient computer program. Keywords: test-pattern calculation. fault modelling. multi-\'alued logic. modelling of logic networks. hardware-description languages, 1. Introduction For the purposes of built-in self testing (BIST), an increasing demand is experienced for possessing efficient test sets that are capable of detecting a wide variety of faults in complex digital circuits. The fulfilment of this demand is especially important in the field of VL51 C~IOS circuits which are rapidly spreading in the modern hardware construction. This paper is intended to present a general test cdculation principle that is suitable for producing tests for a wide range of possible faults: stuck-at-constant logic level (single. multiple). bridging (single). as well as blO-havioural (functionaL single) faults, The proposed principle handles mlllti-\'alued logic, where the number of logic values is unlimited, ",\.11 of those representations are accepted here which operate in the logic domain by ap-plying multi-valued logic, For instance. if the circuit behiwiour is described by the VHDL language [lJ. the logic values will correspond to the signal values in the actual description. ~Ioreover. the le\'el of circuit modelling is also allo\ved to yary in a \\'ide range: switch le\'el. gate leyel. fUllctional level. etc. are equally allowed, (The comprehensive circuit representation based on alternatiye graphs in [2] can also be accepted here.) At the same time. 252 J.SZIRAY the proposed principle is comparatively simple, and it yields an opportunity to be realized by an efficient computer program, both for combinational and for sequential circuits. 2. The Test Calculation Principle The test calculation principle to be presented enables the user to model the digi t al circuits at various levels, namely: • Switch level for :VIOS circuits: the transistors are the building ele-ments . • Gate level: logic gates are applied exclusively. o Functional level: the logic values of an element are calculated 'with knowledge of its external functional behaviour. For this modelling purpose, high level hardware-description languages (HDL's) can be applied. for instance. VHDL. Let the \'ector of primary input and output variables for the complete netv,;ork be .r = (.q, X2 .. .. ,xn ) and 53 = (Z1, Z2," .. zm). respectively. Let the set of possible logic values in the net\vork be F = {l'l. V2 .. •. ,l"s}' In addition to the elements of Y the indifferent or don't care value cl will be applied. Suppose that a sequence of primary input vectors X(t) = .q. :c2 ..... Xi detects q 2: 1 simultaneous faults at a primary output Zj. :-;-ow the task of calculating X(t) can be stated in the following ,","ay. Find a sequence of input patterns \vhich implies Zj = 0 in the fault-free network. and Zj = 3 in the faulty network. where 0 E F. .3 E F. and 0 =!= .1 . To reach this goal, we associate the logic values Lt and J \vith Zj. and attempt to find a sequence of input patterns which equally justifies 1) the normal value of Zj for the normal (fault-free) network. and :2) the faulty value of Zj for the faulty net-,vork. In the first case. X (t) just ifies Z j = 0 through the values of all the necessary network lines in the usual manner. In the second case. ho\\"e\"e1". since the faulty values are self-dependent. they need not be justified by X(t). Thus, in the faulty network. X(t) and the faulty values justify Zj = 3 jointly. The test sequence can be derived by applying the line-value justifi-cation concept. As known. line-value justification is a procedure with the aim of successively assigning input \"alue5 to the logic elements in such Cl way that they are consistent \vith each pre\"ioudy assigned value. (This concept is an auxiliary calculation process for justifying an initial set of logic values in a network, first applied in the D-algorithm for two-valued logic [3]. [4].) In our approach. the computations are carried out simultaneously in the normal and faulty network. i.e .. in the normal and the faulty domain. TEST CALCUL.4TIOS OF COMPLEX DIGIT.4L CIRCUITS 253 Logic values simultaneously representing signal values in both the normal and the faulty networks are called composite values. Line justification performed in terms of composite values is referred to as composite justifi-cation [5]. [6]. The two components of a composite value will be separated by a slash, with the normal component preceding the faulty one. The actual logic value of the i-th line in the network \"ill be denoted by u(i). Then, for example, a composite value of line i is vU) = uJCj . In the composite justification the computational costs can be greatly reduced by the following consideration [5]. The signal values in the normal and faulty net\vorks cannot differ at the lines that do not carry any signals propagating from the sites of the faults. These are called inactive lines, for \vhich C'i =!= l'j would represent inconsistency if they had the composite value of vii L'j. It should be realized that for our purposes it is sufficient to determine which lines (called potentially active lines) carry signals from the faulty lines to :::j. This holds true, since all the other lines in the nehvork are either inactive or are not involved in the justification process. The set of potentially active lines can be generated by intersecting the set of the lines that are reached from the faulty lines with the set of the lines from which Zj can be reached. The two sets are very easy to obtain by topologically tracing out the signal connections. This is done by starting from the faulty lines and proceeding forward. then starting from :::j. and proceeding backward. If a line is encountered in both the forward and backward tracing then it is potentially active. The implementation of the above principle for a synchronous sequen-tial network may require the justification process to be performed through different 5[Orage ~tates of the Ilenvork. \vhich results in a test sequence .Y(t) of length t. The detailed principle of doing it for stuck-at-O / 1 faults is descri bed in In the following. we are going to present the necessary and sumClent conditions for performing the composite justification in case of different fault models. 3. Tests for Different Fault lYlodels 3.1. Shlck-at- Constant Lugic Level Faults An arbitrary signal is erroneously presen-ing a certain logic value (for ex-ample. logic 0 or 1. high impedance value. ete.), independent of the actual control values which may influence the normal value of this signal. Any logic values are allowed \,'ithin rhe range of possible values for that particu-254 J. SZlRAY lar signal. It should be added that not only single faults, but also multiple faults are included. with no limits in their multiplicity. Let the set of lines with stuck faults be denoted by SL, where the number of lines belonging to 5 L is q. If the stuck value at line i of SL is Si. then the initial set of the logic values that are to be justified will be as follows: :::j = 0/.3 for a selected pnmary output. where o E \'. J E V and 0 i= ;3 , and d i) = cl / S i for each i E 5 L In the justification process. the value cl need not be justified. whereas the stuck values Si must not be justified. 3.2. Br£clging (Coupling) FmLits They are defined for two signals. This type of fault occurs when a signal erroneously takes up the normal logic \'alue of another signal. In this case the two signals are said to be bridged (coupled). Only single occurrence is stipulated here for the bridging faults. Let the dominant logic value of t\VO bridged lines be •• :: It means that the '."alue w' will appear on both lines. instead of the normal different ,'alues. If the bridged lines are b1 and b2 then the initial values for the composite justification ,,;ill be as follows: :::j = 0/:3 for a selected pnmary output. where J E \' and 0 =f 3 . and c(bl) = db2 ) = rI/w' . In the justification process. the following measures have to be taken for the bridged lines: a) If either of them is reached by a determined logic value (i.e .. Cl value other than cl) in the normal domain, then the value of the other bridged line mus t be set to •• ; / v.:. b) If in a backtrack process. bl or b2 is reached. then the initial value cl/wo has to be assigned to both lines again. as the solution when can-celling the former decisions. i.e .. \vhen cancelling the former calculated logic values. TEST G.4LCc·L.4TIOS OF CO~rpLEX DIGlT.4L CIRCUITS 255 s.s. Behavioural (Punctional) Faults This type of fault is related to a logic module j\;I; for which the faulty behaviour is to be previously defined by the user. The definition can be made by means of a high level HDL (e.g .. VHDL), where the faulty output responses are gi"ven explicitly, at the presence of the faultless input signals or the faultless input sequence obtained by AI;. In our case, only single-module faults will be handled at a time. The initial values to be justified are: Zj = 0/3 for a selected pnmary output. where o E 1i, 13 E 1/- and 0 =I- ,13 1 and the input/output signals of !H; in the normal domain. as well as the faulty output signals of IvIi in the faulty domain. S.4. Switch Level Faults The fault model of MOS circuits includes stuck-at-1/0 logic faults on the connecting lines, and switch faults in the transistors: stuck open (the tran-sistor is erroneously in an open circuit state), and stuck short (the transistor is erroneously in a short circuit state). The paper [7] describes a procedure to convert a transistor structure into an equivalent logic gate structure. In this way the transistor faults can be converted to stuck faults in the logic structure. All this makes it possible to use composite justification for single and multiple faults in :\10S circuits, without any modifications. On the other hand, it is also possible to apply the direct sv;itch level (transistor) structure when performing composite justification. Here the initial settings are: Zj = a/ f3 for a selected primary output, where a =I- ,B. The possible values for a and f3 are logic 0 and 1, as well as high impedance state (Z). Furthermore, the faulty transistors are to be JI1 their faulty state (open or short) in the faulty domain. In this approach line justification involves the tracing back of the pos-sible switching paths through the transistors in the circuit. The detailed description of the algorithm exceeds the frames of this paper. 256 J. SZIRA Y 4. Concluding Remarks This paper has been meant for showing how the test calculation algorithm first published in [5] can be generalized for a wide range of fault models and circuit models. The flexibility of the composite justification is based on the fact that it establishes the minimal necessary and sufficient set of logic values which yield the test conditions for the faults. As seen, the tests are obtained by justifying the initial logic conditions. The salient advantage of composite justification is the total absence of the fault propagation phase. This feature makes the approach extremely flexible in terms of circuit modelling and fault classes. The same applies to the use of an HDL [8], [9]. As known, the fault propagation phase. i.e .. D-propagation is an inherent part of the \vide-spread D-algorithm [3] [4], \vhere this phase implies serious difficulties for functional level models and multiple faults. The test generation algorithm called PODE?vI (Path-Oriented DEci-sion Making) [11], [12] was shown to be more efficient than the D-algorithm. The improvement is related to the decision tree of the line justification, in that the PODE?vI algorithm has indeed succeeded in reducing the oc-currences of backtraces, in comparison with the D-algorithm. In the D-algorithm, since the assignment of values is allowed to internal lines, more than one choice is available at each internal line or gate, and backtracking could occur at each gate. In contrast. the PODElvI algorithm allows assign-ing values only to primary inputs. The values assigned to primary inputs are then propagated toward internal lines by the logic implication. Thus, in this approach, backtracking can occur only at the primary inputs. The results achieved in the PODE)'! algorithm can be further im-proved, since there still remained many possibilities of reducing the number of backtracks in the algorithm. Such an improvement has been the FA:\, algorithm [13], [14]. The fanout-oriented test-generation algorithm FA:i traces out the structure of the network. in order to find the nonexistence of the solution as soon as possible. Also. logic implication is widely involved in the procedure. On the other hand. the acceleration results in the PODE::vr and FA:i algorithms are relied on the use of the gate-level ner-work structure [12]. However, if functional level modelling is considered then the structural and logic analyses performed in both algorithms become extremely cumbersome and hardly feasible. In contrast. the approaches based on composite justi-fication are not really limited by the way of network modelling. The same is applied to the network types. i.e .. combinational or sequential. and also. the types and multiplicity of the faults. As far as the computer implementation is concerned. only line justi-fication is to be accomplished in the presented principle, which is also an advantage. In order to perform the line-value justification. the inverse models of the building elements in the network are required. An inverse TEST C.4LCUL.4TION OF COMPLEX DIGITAL CIRCUITS 257 model defines the set of possible input patterns which result in a specific state or an output pattern [8], [lOJ. For this purpose, high level hardware-description languages, such as VHDL, can also be applied [9J. The computerized implementation of the proposed principle will handle multi-valued logic, \vhere the number of logic values corresponds to the number of the possible signal values in the HDL applied for modelling [8], [9J. The complexity of a logic module is not limited in principle. Only practical trade-offs, such as processing time, and user efforts in terms of modelling accuracy are to be considered. Acknow ledgement The author \vishes to thank Dr. Andnis Pataricza for his valuable advice in prepar-ing the present paper. References [lJ NAVABI, Z.: VHDL: Analysis and ~lodeling of Digital Systems, McGraw-Hill, Inc., USA,1993. [2J UBAR, R.: Test Generation for Digital Systems Based on Alternative Graphs, De-pendable Computing - EDCC-1 (Ed. by D. Echtle, D. Hammer and D. Powell), pp. 1.51-164, Springer-Verlag, Berlin, 1994. [3J ROTH, J. P.: Diagnosis of Automata Failures: a Calculation and a Method. IBM Journal of Research and Development, Vol. 10, pp. 278-291, July 1966. [4J BREUER, M. A. - FRIED:VIAN, A. D.: Diagnosis and Reliable Design of Digital Systems, Computer Science Press. USA, 1976. [.5J SZIRAY, .1.: Test Calculation for Logic Networks by Composite Justification. Digital Processes, Vol. .5, No. 1-2. pp. 3-1.5, 1979. [6J SZIRAY. J.: Functional Le\'el Test Calculation and Fault Simulation for Logic Net-works, Discrete Simulation and Related Fields (Ed. by A. Javor), pp. 223-234. North-Holland Publishing Company, Amsterdam, 1982. [7J JAIN. S. K. - AGRAWAL, V. D.: .\lodeling and Test Generation Algorithms for .\1OS Circuits, IEEE Trans. on Computers, Vol. C-34, pp. 426-433, '\Iay 198.5. [8] SZIRAY, .J. - NAGY. Zs.: OPART: A Hardware-Description Language for Test Gen-eration, Microprocessing and .\Iicroprogramming. (Ed. by P. Nunez), pp . .52.5--530. North-Holland Publishing Companv. Amsterdam. 1991. [9] SALLAY. B. TILLY. I<. .. - PAT.'\RICZA. A. . CSERT.~N, G. - HEGEDl's. Z. -PETRI. A. - SURJ . .\.;\', L. SZIRAY, J.: A Proposed VHDL Subset for Test Gen-eration Purposes, Technical Report FUTEG-1/1994, PECO 9624 Project. Budapest. 1994. [10] BREUER, M. A. - FRIEDMA;\', A. D.: Functional Level Primitives in Test Generation. IEEE Trans. on Computers, Vo!. C-29, pp. 223-23.5, March 1980. [11] GOEL, P.: An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits, IEEE Trans. on Computers, Vol. C-:30, pp. 21.5-222, March 1981. [12] ABRA:VlOVICI, M. - BREUER, M. A. FRIEDMAN, A. D.: Digital Systems Testing and Testable Desicrn, Computer Science Press, USA, 1990. [13J FUJIWARA, H. S'HIMONO T.: On the Acceleration of Test Generation Algorithms. IEEE Trans. on Computers, Vol. C-32, pp. 11:37-1144, December 1983. [14J FUJIWARA, H.: Logic Testing and Design for Testability, The MIT Press, USA. 198.5. 

A COMPREHENSIVE METHOD FOR THE TEST CALCULATION OF COMPLEX DIGITAL CIRCUITS

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A COMPREHENSIVE METHOD FOR THE TEST CALCULATION OF COMPLEX DIGITAL CIRCUITS

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