Csanky, L.

English

Periodica Polytechnica (Budapest University of Technology and Economics)

A NEW NOT -AND-EXCL USIVE OR GATE By L. CSANKY Department of Process Control, Technical "Cniversity, Budapest (Received Noyember, 1, 1968) Presented by Prof. Dr. A. FRIGYES Introduction The technique of expressing Boolean functions in terms of EXCLUSIVE OR and AND operations has been examined by REED [1] and MULLER [2, 3]. Both haye shown that a function of 71 logical yariables may be expressed in the following canonical form: (1) For example the canonical form for a three-yariable logical function IS: F(x) COH:" [4] has shown that the replacement, consistently throughout such a form, of any yariable by its complcment should yield an equally yalid cano-nical form. The coefficients hi for a giyen function may he altered. If all the variables are replaced by their complements, the canonical form will be: (3) Consequently. any logical function can be realized by the I\OT-_·L\"D-EXCLl-SIYE OR gatf'. The logical realization of the NOT-AND-EXCLUSIVE OR gate The logical diagram of the gate is shown in Fig. 1. The output logical function F: + x:!~ -:- ... --: (4) a =a b=a b (5) 138 L. CS.·nKY Xi Fig. 1 Thus F=x1 Applying thc Dc Morgan theorems r +X::!~ + ... - (6) Thus the gate in Fig. 1 operates as a "NOT-A~D-E::'\.CLLSIYE OR gate. Let the symhol in Fig. 2. stand for the ~OT-A~D-E::'\.CLLSIYE OR gate. r Fig. 2 If such gatcs arc connected in cascade by the in put Xl and the out put F, as shown in Fig. 3, then the output function will be: F (8) ~oticeahly the algebraic form for the output F (8) is conformahle to the canonical form (3), hence any logical function of not more than It variables can be realizcd hy the gates in Fig. 3. r Fig . .1 139 The realization of the NOT·Al~D·EXCLUSIVE OR gate The eircuit realizing the :\"OT-AND-EXCLUSIYE OR gate is shown III Fig. -1. r----------.---oU,! r-----~--o G Fig . . [ The operation of the eireuit: Transistor T3 operates as an output inYcTter and in addition performs the signal standardization. Transistors Tl and T~ form an EXCLDSIYE OR eireuit, in 'whieh trall-;;istor T ~ is so arranged that it ean operate a;; an OR-~OT gate too. The EXCL C-SIYE OR eireuit is sho'wn in Fig. J. ;----0;;; Gxz '----;------<> UiZ X2 Fig . .5 The operation of the EXCLLSIVE OR eireuit: Let "not" leyel (OV) be at the input X~. In that ease transistor T ~ is eut off, hence transistor Tl goes into saturation independently of the Xl value, and the yalue of Xl appears at its eolleetor. Thus transistor Tl operates as a follower. Let "yes" level (- 3Y) be at the input x!, In that ease transistor T ~ goes 2* 140 L. CSANKY into saturation and switches the emitter of transistor Tl to zero volts. Thus transistor Tl operates as an inverter. The operation of the OR-NOT gate formed from the transistor T z and the operation of the output inverter is of common knowledge. The design of the NOT-AND-EXCLUSIVE OR gate The folIo'wing transistors are chosen: Tl OC 44 K. T z OC 44 K. T3 OC 1072 Be: U10g = -3Y UTl -7.5Y UT'! +7.5V The design method of the OR-NOT gate formed from transistor T 2 is well known. The design of the EXCLUSIVE OR circuit If transistor Tl operates as an inverter and is eut off, then the current through resistor R2 should he sufficient for the saturation of transistor T 3• According to the characteristics of the transistor T3 , - la = 0.2 mA is sufficient for the saturation, if R4 > 1 kQ. Thus U-R,,= __ ll_ -7.5V = 37.5 kQ - Is -0.2 IllA The restriction on the value of resistor R4 is realized if the value Rz = 33 kQ is chosen. If transistor Tl operates as an inverter, and there is "'yes" level at the input Xl' then the value of resistor Rl is restricted hy the maximum hase current of transistor T 1• = 10kD A SElF SOT-A;'-D-EXCLCSIVE OR GATE 141 Let the value RI = 10 k..Q be chosen. If transistor TI operates as a follower, and there is "not" level at the input Xl' then the restriction on the collector voltage of transistor T 1 : Uc 0 Transistor TI operating as a follower may be regarded as a short circuit in first approximation, as shown in Fig. 6 . .------.... un L-----.... UT2 Fig_ 6 If the value IS chosen, the restriction (9) is realized. If transistor TI operates as a follower and there is "yes" Ipn·l at tlw in put Xl. then Uc be sufficient for the saturation of transi;;to1" Ta. In that case: u c The internal resistance: Thus the base current of transistor T3: I _ -1.5 V-B- 6M2 -1.5 V -!.-0.2 V 6kQ O.2l7mA And this is sufficient to saturate transistor Ta' jf R4 > 1 kQ. The design of the output inverter: 142 The yalue of rf'si5tor R4 is chosen under the condition that the :NOT-A~D­EXCLlJ5IYE OR gates can be connected into cascade. If transi5tor TI operates as an inverter and is in saturation: RI R Un II = --- = -7.5Y = 25kQ IB:"vl -0.3 IllA Thus If transistor Tl operates as a follower and transistor T3 of the preyious stage is cut off: F nR3 - U nR2 X (RI + R.I ) R3 + R2 )< (RI + R 4) 9.35 kQ Thus the base current of transistor T3 is: 2.33 Y - UBE 9.35 kQ ~''::' -2.33 Y - 0.2 Y 9.35kQ - 2.33 Y - 0.277 IllA And this is sufficient to saturate transistor T 3 , because R4> 1 kD. 50 the yalue of resistor R4 may be: RJ = 15 kD Summary This paper report-; on a nc,,· circuit realizing the ~OT-A~D-EXCLLSIYE OR giltC· The relatiyely eC(Jnomical solution ,,·as obtained by the multiple exploitation of the lran,j,tors. References 1. REED, I. S.: A cla;;s of multiple-error-correcting codes and the decoding scheme. Tran,. Inst. Radio Engrs 1T-4 38-49 (1954). 2. }Il"LLER, D. E.: Metric properties of Boolean algebra and their application to switching circuits. Uniy. of Ill., Digital Computer Lab., Internal Report ~o ... B, 1953. 3. }IuLLER, D. E.: _-\pplications of Boolean algebra to switching circuits design and error detection. Tram. Inst. Radio Engrs EC-3 6-12 (1954) . .. 1. Conl>, 1\I.: Inconsistent canonical forms of switching functions. Trans. on Electronic Com-pnters 284-285 (1962). La5z16 CSA::\"KY. Budape5t XI., }1(iegyetelll rkp. 9. Hungary. 

A NEW NOT-AND-EXCLUSIVE OR GATE

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A NEW NOT-AND-EXCLUSIVE OR GATE

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Periodica Polytechnica (Budapest University of Technology and Economics)