Csanky, L.

English

Periodica Polytechnica (Budapest University of Technology and Economics)

NEW EXCLUSIVE OR CIRCUITS USING CONTROLLED TRANSISTOR INVERTERS By L. CSA:,{KY Department of Process Control, Technical University. Budapest (Received September 18. 1968.) Presented by Prof. Dr. _-\. FRIGYES Introduction The definition of Exclusive OR operation: The definition of equivalence operation: Both operations arc associative: that is: Both operations are cornmutativ,>. that is: Relations bl'tween the Exclusive OR and equivalence operations: TIlt' output of an 11 input Exclusiyt' OR gate: 1 2 Pt'riodi<:<t POiYll'chni('u El. 13/1-:! ( 1) ( 2) (3) (4) (7) (8) (9) 18 I .. CSA.YKY where: k = the number of logical variables Xi equal to 1 n-k = the number of logical variables Xi equal to 0 p = positive integer The relation (9) shows that the logical value of the output function of n variables can be obtained by the examination of parity. The output of an n input equivalence gate: a) If n = 2m, then: b) If n 2m -'- 1. thcn: fl if k 2p 10 if k = 2p -~ 1 f1 if k = 2p --1 to if k = 2p where: k = the number of logical variables Xi equal to 1 n-k = the number of logical variables X, equal to O. rn, p = positive integers (10) (11) The relations (9), (10), (11) can easily he proved hy the definitions and identities in (1) through (8). In consequence of the relations (9) and (11): (12 ) In consequence of the relation;; (9) and (10): (13 ) Let the eontrolled inverter be defined as a two input one output logical circuit, ,,,-hich operates either as an inverter or a follower betwcen the other input and the output depending on the value of logical variable at the control input. It is easy to demonstrate, comparing the definition of controlled inverter and the dcfinitions in (1), (2), that both the Exclusive OR and the equivalence operations can be realized by controlled inverter. The symbol for a controlled inverter realizing the Exclusin' OR opera-tion and its operation table arc shown in Fig. 1. The symbol for a controlled inverter realizing the equivalence operation and its operation table are shown in Fig. 2. _,"Ell? ESCLl"nE OR URCl!T" 19 XI X2 Operation r 0 0 Follower 0 1 0 Follower 1 0 1 Inverter 1 1 1 Inverter 0 Fig. XI X2 Opera/ion F rVt-__ r;XI0X2 0 0 Inverter f r 0 Inverter 0 0 1 Follower 0 1 1 Follower 1 X2 control Input Fig. -') ! -j ;1 -"rV--rO---rD---r-[)---.' "2 ,~] \ ,{n Fig. 3 Tht' difference between the t,,-o controlled inverters is that the control logical variables belonging to the same operation are the complements of paeh other. Sincc both the Exclusive OR and the equivalence operations are associa-tive, in the case of n input logical variables (n -1) controlled inverters connect-ed in cascade rpalizc the output logical function F, a~ it is shown in Fig. 3. The realization of controlled inverter The operation of the described circuits is based OIl the fact that thc transistor gains also if the emitter and the collector an~ commuted mutually, although its inherent current gain drops off. These circuits form negative logic, but positive logic can be realized as well, if the transistor types are changed from PNP to NPN. A possible controlled inverter circuit realizing the Exclusive OR opera-tion is shown in Fig. 4. 2* 20 L. CS.-L'E Y r-------------------------o-ur Xi C>----l ___ J--"+---i., r = Xi El X2 ~-----~ o---4----------~~------_+----------._--~O X2 Fig. -1 The operation of principle of the circuit in Fig. 4 Let "non" level be at the control input X 2 • In that ease transistor Tl IS cut off, the emitter of transistor T-:. is eonnected to negatiye yoltage by resistor R 2, the collector of transistor T z is connected to zero yolts by resistor R 3 • Thus the transistor Tz operates as a follower between the input Xl and the output F. Let "yes" level be at the control input x 2 • In that case transistor Tl goes into saturation and switches the emitter of transistor T z to a yoltage of about zero volts, the collector of transistor T z is connected to th(' negative voltage at the control input X 2 by resistor R 3 • Thus the transistor Tz operates as an inverter between the input Xl and the output F. In this circuit the current gain of transistor T z is low, when it operate" as a follower, and high, when it operates as an in HTter. Another possible controlled inverter cireuit realizing the Exclu~iYt' OR operation is shown in Fig. 5. r---------------------o-ur i. O--;--------~~----_+------~----oO Fig . .5 .YErr· EXCLUSIfE OR CIRCUTS 21 The operation of principle of the circuit in Fig. 5 Let "uon" level be at the control input Xl' In that case transistor TI is cut off, the collector of transistor T2, is connected to negative voltage by resistor R 2 , the emitter of transistor T'!, is connected to zero volts by resistor R 3 • Thus the transistor T2 operates as a follower bet·ween the input Xl and the output F. Let "yes" level be at the control input x 2• In that case transistor T2 goes into saturation and switches the collector of transistor T'!, to a voltage ...------------_0 - UT F= X, 8,-(2 ~~~---------+------~--------~--~o Fig. 6 of about zero volts, the emitter of transistor T z is connected to the negative voltage at the control input X z by resistor R 3• Thus the transistor Tz operates as an inverter between the input Xl and the output F. In this circuit the current gain of transistor T2 is high, when it operates as a follower, and low, ·when it operates as an inverter. A possible controlled inverter circuit realizing the equivalence operation is shown in Fig. 6. The operation of principle of the circuit in Fig. 6 Let "non" level be at the control input X z. In that case transistor TI is cut off, the collector of transistor T'!, is connected to negative voltage by re-sistors Rz and R 3 , the emitter of transistor Tl is connected to zero volts. Thus the transistor T2 operates as an inverter between the input Xl and the output F. Let "yes" level be at the control input Xl' In that case transistor TI goes into saturation and switches the collector of transistor T z to a voltage of about zero volts through resistor R 3 , the emitter of transistor T2 is connected to the negative voltage at the control input x 2 • Thus transistor T z operates as a foUo·w-er between the input Xl and the output F. 22 In this circuit the current gain of transistor T'}. is high, when it operates as an inverter, and low, when it operates as a follower. Another possible controlled inverter circuit realizing the f'quivalence operation is shown in Fig. 7. t X,0 X2 /;<>----1, Fig. -The operation of principle of the circuit in Fig. 7 Let "non" leyel be at the control input xc.!' In that case transistor Tl i::: cut off, the emitter of transistor T2 is connected to negatiyC' yoltagf' hy resi:::tors R:! and R 3 , thf' collector of transi:::tor T:! is connected to zero volts. ThuE'. transistor T2 operates as an inverter between the input Xl and the output F. Let "yes" level be at the control input x:!, In that caEe transistor '1'1 goes into saturation and s'witche5 the emitter of transistor T:! to a voltage of about zero volts through n'5[stor R;l' the collector of transistor T2 is COllllect-ed to the negative voltage at the control input x:!, Thus. transistor T:! operates as a follower between the input Xl and the output F. In this circuit the current gain of transistor T:! is IO\L 'when it operatei' as an inverter, high, when it operates as a follower. In all the four circuits the function of resistor R: is to increase the low ontp~t resistance of the controlled inverter. when it operates as a foIlo'wer and the lo'w input resistance of the controlled inverter, 'when it operates as an inverter. Anyone of these circuits connected in cascade as it is shown in Fig. 3 requires a signal standardization, hecausf' of the less than OIlt' yoltage gam of the controlled inverters operating as foIlo·wer::::. NEW EXCLUSIVE OR CIRCUITS 23 The design of controlled inverter As an example let an n = 8 input Exclusive OR gate be designed. Let the type-circuit in Fig. 6 be chosen. The number of necessary controlled inverters: In consequence of Eq. (13) the circuit standardizing the output signal will be an inverter. la 100,----[;..;/y 50 f---------0,05 0,1 0,15 {)2 {)25 UcaM Fig. 8 The drop of logical level is the highest. ·when all the seven controllf~d inverters operate as followers. As 1.4 V is sufficient to have the output inverter operated, the permissible drop of logical level across the seven controlled inverter;:: lA Y 3 Y - lA Y 1.6 Y where: Flog = the logical "ye,;" level The permissible drop of logical level across one controlled ill,-erter: F . _ 1.6 F U d'l stage - -_-. - y i 0.23 V Let this value be regarded as the highest permissihle voltage drop across anv one of the scven controlled inverters. The following transistors are chosen: Tl = OC 1045 Tee. = OC 1044 The characteristics of transistor T~ must be measured, commuted the emitter and the collector of transistor. 24 L. CSA"KY The characteristics lB = lB(UcB) is shown in Fig. 8, the directions of currents and polarity of yoltages are sho'wn in Fig. 9. The characteristics lE = fe(I B): 2, if UCE = 0.2 Y 2-3, if UCE 0.2 V - 3 V u~ Fig. 9 The transistor OC 1044 enduring a base current of about 280 ,uA, the value of resistor R4 can be 10 kD. So, if anyone of the seven controlled inver-ters operates as a follower, the following one as an inverter, the base current will be: 98 V ?S ~. = 280 uA 10kQ ' The value of resistor RI being given, the characteristics of resistor R.j can be drawn in the characteristics lH = ljj(UcH ). Segments: U CB = U dilstage = 0.23 V 0.23 V = 23 uA 10kQ ' The point of intersection of the two characteristics: UCH = 0.09 Y lH = 14,uA The emitter current calculated by an average value j3 = 2.5 fe = j3 lH = 2.5 . 14 ,uA = 35 ,uA :VErv EXCLUSIVE OR CIRCUITS 25 The collector current: For the transistor T2 of the following controlled inverter also consumes base current, the collector current will be: Ic=Ic Thus the value of resistor R3: R -. U 10g - Ud!lstage 3-Ic 3V - 0.23 V ----- = 80 kQ . 0.035 mA If in all the seven controlled inverters the value of resistor R3 is 80 kD, the voltage drop across one controlled inverter will not be constant, it is the highest across the first and the lowest across the seventh controlled inverter. The value of resistor RI is chosen so that the logical "yes" level at the control input X z saturates transistor T 1• The base current necessary to satu-rate transistor T 1 : Thus: 3V RI = ---- = 20kD 0.15 mA Let the value of resistor R z be: R:!. = 10 kD Thus UCE is practically zero volts for UT < 20 Y. The evaluation of supply voltage If both transistors TI and T:!. are cut off, the current through resistors R2, R 3, R.I should be sufficient to the saturation of transistor T2 of the following controlled inverter, which operates as an inverter. The base current necessary to the saturation of transistor T 2 : IH ?c'"' 100 pA Thus the supply voltage: UT = IH(R!. UT = 10 Y 82 + 10) kD 26 L. CS.4.YKY Summary This paper reports on four new circuits realizing the Exclusive OR operation. The circuits are based on the fact, that the transistor also gains, when the emitter and collector are commuted mutually. Therefore the usual inverter operates as a follower, if the polarity of supply voltage is changed. Liisz16 CSANKY, Budapest XL Miiegyetem rkp. 9. Hungary 

NEW EXCLUSIVE OR CIRCUITS USING CONTROLLED TRANSISTOR INVERTERS

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NEW EXCLUSIVE OR CIRCUITS USING CONTROLLED TRANSISTOR INVERTERS

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Periodica Polytechnica (Budapest University of Technology and Economics)