A realization of a division algorithm suitable for high speed pipeline and realtime processors is presented. Implementation of the divide algorithm can be achieved by utilizing LSI / VLSI gate array technology. The divider performs precision, high speed 9 bit sign magnitude division. The design consist of combinational logic, where input and output data are latched into input and output registers. Data propagates through 16 divide stages. The n\u27th stage generates the n\u27th quotient bit upon receiving the updated dividend and controls from the previous stage. A simulation program is developed to verify the algorithm, and an analysis for speed performance and cost is provided. Other division algorithms are discussed
