Cerium dioxide was employed as a gate insulator for an enhancement-type n-channel metal-oxide-semiconductor (MOS) transistor. Cerium was evaporated in a tungsten boat and immediately oxidized for oxide uniformity. The use of CeO2 as a gate oxide in MOS transistor yielded a low positive threshold voltage with negligible interface charge effects. This resulted in the transistor performing as an enhancement type device

Frangoul, A. G.

Sundaram, K. B.

Wahid, P. F.

English

University of Central Florida (UCF): STARS (Showcase of Text, Archives, Research & Scholarship)

University of Central Florida STARS Faculty Bibliography 1990s Faculty Bibliography 1-1-1991 The Fabrication Of Metal-Oxide Semiconductor Transistors Using Cerium Dioxide As A Gate Oxide Material A. G. Frangoul University of Central Florida K. B. Sundaram University of Central Florida P. F. Wahid University of Central Florida Find similar works at: https://stars.library.ucf.edu/facultybib1990 University of Central Florida Libraries http://library.ucf.edu This Note is brought to you for free and open access by the Faculty Bibliography at STARS. It has been accepted for inclusion in Faculty Bibliography 1990s by an authorized administrator of STARS. For more information, please contact STARS@ucf.edu. Recommended Citation Frangoul, A. G.; Sundaram, K. B.; and Wahid, P. F., "The Fabrication Of Metal-Oxide Semiconductor Transistors Using Cerium Dioxide As A Gate Oxide Material" (1991). Faculty Bibliography 1990s. 229. https://stars.library.ucf.edu/facultybib1990/229 The fabrication of metal–oxide–semiconductor transistors using cerium dioxide as agate oxide materialA. G. Frangoul, K. B. Sundaram, and P. F. WahidCitation: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing,Measurement, and Phenomena 9, 181 (1991); doi: 10.1116/1.585285View online: https://doi.org/10.1116/1.585285View Table of Contents: https://avs.scitation.org/toc/jvn/9/1Published by the American Institute of PhysicsARTICLES YOU MAY BE INTERESTED INFabrication of n-metal–oxide semiconductor field effect transistor with Ta2O5 gate oxide prepared by plasmaenhanced metalorganic chemical vapor depositionJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing,Measurement, and Phenomena 12, 3006 (1994); https://doi.org/10.1116/1.587550Fabrication of metal–oxide–semiconductor devices with extreme ultraviolet lithographyJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing,Measurement, and Phenomena 14, 4188 (1996); https://doi.org/10.1116/1.588618High-κ gate dielectrics: Current status and materials properties considerationsJournal of Applied Physics 89, 5243 (2001); https://doi.org/10.1063/1.1361065Violet/blue emission from epitaxial cerium oxide films on silicon substratesApplied Physics Letters 70, 1647 (1997); https://doi.org/10.1063/1.118658Erratum: Asymmetry aberrations and tolerancing of complete systems of electron lenses and deflectors [J. Vac.Sci. Technol. B 8, 1676 (1990)]Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing,Measurement, and Phenomena 9, 184 (1991); https://doi.org/10.1116/1.585783Cerium oxide nanoparticles: Size-selective formation and structure analysisApplied Physics Letters 80, 127 (2002); https://doi.org/10.1063/1.1430502BRIEF REPORT AND COMMENT This section is intended for the publication of (l) brief reports which do not require the forma! structure of regular journal articles, and (2j comments on items previously published in the journal. The fabrication of metal-oxide-semiconductor transistors using cerium dioxide as a gate oxide material A. G. Frangoul, K B. Sundaram, and P. F. Wahid Department a/Electrical Engineering, Universityo/Central Florida, Orlando, Florida 32816 (Received 7 May 1990; accepted 26 October 1990) Cerium dioxide was employed as a gate insulator for an enhancement-type n-channel metal-oxide-semiconductor (MOS) transistor. Cerium was evaporated in a tungsten boat and immediately oxidized for oxide uniformity. The use of CeOz as a gate oxide in MOS transistor yielded a low positive threshold voltage with negligible interface charge effects. This resulted in the transistor performing as an enhancement type device. I. INTRODUCTION Research in various elemental compounds as insulating ox-ides has led to their potential use in thin film devices and has marked possibilities in very large scale integrated (VLSI) material technology. 1,2 Quality thin film insulating materi-als are an important factor in the design and operation of monolithic and hybrid devices. They enable device size re-duction and their intrinsic dielectric properties can be used to obtain the required characteristics in various microelec-tronic devices. Thin films of cerium dioxide (Ce02 ), a rare earth oxide, have received attention in the recent years due the high dielectric constant and the potential use of these films in thin film devices. Cerium dioxide exhibits a strong dielectric breakdown field with values on the order of 107 V Icm. Information regarding the electrical and optical properties ofCe02 available in the literature3.4 has had influ-ence on its possible use in metal-oxide-semiconductor (MOS) devices. In metal-oxide-semiconductor devices, the oxide affects parameters such as the threshold voltage ( V T ) and the small signal transconductance (gm)' For devices using thin film oxides in the range 0.02-0.2 pm, it becomes necessary to realize the differences that stem from the use of different types of oxides. The threshold voltage VT of a MOS transistor is depen-dent on the type of gate oxide material used. Certain applica-tions require not only a low value of V T' but also a precisely controlled value to match to other devices in the circuit. Use of oxides such as Si3N4 and Si02 in devices have been report-ed.5 Si3N4 has a relative dielectric constant of approximately 7 compared to 3.9 ofSi02• Studies on Ceo2 show that it has a relative dielectric constant of 4.2 at room temperature, which is slightly higher than 8i02• With higher relative di-electric constant materials the gate capacitance can be in-creased thereby reducing V T' Even though Si3N4 has a high dielectric constant, it has the disadvantage of contributing charges at the oxide-nitride layer which affect VT directly. This charge formation is what causes most Si02 MOS n-channel enhancement devices to operate in a depletion mode. In the devices fabricated here, CeOz is deposited on the Si substrate and there is no ionic formation due to Si02 growth. The application of Ce02 in AI-Ce02-Si enhancement-type n-channel structures is investigated here. The fabrica-tion techniques employed are filament evaporation and de-position of cerium metal (Ce) and subsequent oxidation to get ce02 as the gate oxide. The quality of this oxide is ana-lyzed and directly related to the study of how it will influence the device characteristics and operation. In this paper, the r-- ": __ -,====--~~-.-_:::::J 1) DRY OXIDATIO~ '>""ceoo5 2) NEG. PR 'PROC~--" --------.. __ ..... ~----3) EXPOS, USING i.lASK " 4) OEVELOP 5) ETCH SiOi 6) REMOVE PR n DiffUSE PrlOSPHOR._CU_S __ Ie} POSITIVE PR PROCESS II l EXPOSE USING MASK ,1 12( DEVELOP 13, rTCH 5101 14) DEPOS:T Ce 1~} REMOVE POS:TIVE PR LIFTOFF PROCl:SS ___ L_.¢_'-'~~~-":~_'--=--'_/.-~-'0~_.~ ____ .... _-_I _1-,€}_O_X_'D'_ZE_C_"_'N_.ro_c_.e_o, __ 17) NEGATVE' PH "ROC! SS ~ '\ ~'" ~:""2 IS) EXPOSE USING MASK, 2 .. 19) DEYCLOP L ..... _~ ' .. _~ .. ' ""_ .. ,_.:._3_-, 20) rTCH SiO'-. 21) REMOVE PR __ .. ___ .... __ ..... __ ._. . 22)"OE.".o.?'!ftL .. ____ _ {CI (01 (,.1 23) NEGA fiVE PR PROCESS 24) EXF10Sf USING MASK ~3 20) DEVELOP 26) ueH AI 27) REMOVE I'R FIG. I. Fabrication sequence for the MOS transistor. 181 J. Vac. Sci. Techno!. B 9 (1), Jan/Feb 1991 0734-211 X/91/010181-03$Ol.00 © 1991 American Vacuum Society 181 182 Frangoul, Sundaram, and Wahid: MOS transistors using cerium dioxide 182 .7 .6 .5 .-Io .4 (rnA) ,3 -.2 .1 la) (bl --___ ------.- V's" .7SV ______________ Ike = .74V ~ __ ------_ Ves =: .71 V _______ ·_V"" .68V ______ 1/;;, co .65V ------ VesOO .62V ____ .. --__________ Ves" .59V .-+---1-+---1---.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Vos (Volls) FIG. 2. (a) Plot of If) vs Vns . (b) Photograph of the I" vs VDS curve. effect of Ce02 on the MOS threshold voltage and the gate capacitance are reported. II. EXPERIMENTAL The device was fabricated on a 2 in. p-type Si wafer with a (l00) orientation and a resistivity between 8-15 n cm. The substrate was cleaned with trichloroethylene, acetone, methanol and deionized water with a resistivity of 17.7 MO cm. The wafer was then placed in sulfuric peroxide cleaner following a "hot etch" (6NH4F: 1 BF). After proper masking sequences, the source and drain regions were opened for the predeposition of phosphorous. Solid solubil-ity concentration was achieved in a diffusion furnace at 900°C for 20 min. This was followed by a drive-in step, a dry-wet-dry oxidation sequence, each of 10 min duration, at 1100°C. The carrier gas for dry oxidation was oxygen and nitrogen was used for the wet oxidation. A second masking sequence for the gate region was performed, wherein the area over which Ce02 was to be deposited was etched thor-oughly ofSi02 in a hot etch solution. Ce was then deposited by filament evaporation using a tungsten boat in a cryogenic pump vacuum system. Approximately 70 mg of Ce was e-vaporated on the wafer in a vacuum of 1 X 10 5 Torr. Sever-al thickness measurements were made over the 2 in. diam Si wafer using an optical interferometer. The measurements resulted in thickness variations of ± 100 A. The wafer was placed at a distance of 20 cm from the fiiament evaporator using a glass chimney. Ce deposited on areas other than the gate region was removed by a lift -off process. The wafer was then placed in a dry oxidation furnace and the complete oxi-dation of the cerium film was achieved in 10 min at 400 "C J. Vac. Sci. Technol. B, Vol. 9, No.1, Jan/Feb 1991 09°1 0.8°1 07°1 0.601 %0.50. 1/2 : mA 0.40 (al fb) 0.30 0.20 0101 0.00-'-- -, 0.00 0.10 ,i/ / J' / " ,,/ F1G. 3.(a) Plot of I ',;' vs V"s' (b) Photograph offf) vs Vus' with a constant flow of 02' The oxidation uniformity was excellent, as indicated by optical measurements done on these films. A third masking step was performed on the source and drain for the opening of the contact windows. Aluminum was then deposited by thermal evaporation in the cyro pumped vacuum system. The fourth masking step was done to define the contacts, where Al was etched in a solu-tion of phosphoric acid and deionized water (one part phos-phoric to three parts deionized water) and heated to about 90"C. The Al etchant does not attack Ce02 as it can be etched only by buffered hydrofluoric acid. Figure 1 outlines the fabrication process employed. III. RESULTS The CeOz n-type enhancement MOS transistors were fab-ricated with a gate oxide thickness of 0.16 {-tm on a silicon substrate with a 000) orientation. The gate width was 200flm. A HP 177 curve tracer was used to measure the character-istics of the devices. Figure 2 (a) shows typical characteristic curves. These curves were redrawn, for clarity, from the photographs shown in Fig. 2 (b) taken from the curve tracer. Figure 3(a) shows the square root of the drain current ver-sus the gate voltage redrawn from photographs shown in Fig. 3 (b). The threshold voltage determined from this graph shows a value of approximately 0.3 V. This value is represen-tative of a number of samples measured on a typical 2 cm X 2 cm Si substrate. A MOS device with a Si02 gate ofthickness ·····1··· 183 Frangoul, Sundaram, and Wahid: MOS transistors using cerium dioxide 183 0.16 pm grown on a (100) substrate orientation has a threshold voltage of approximately - 2.4 V. Such a large negative threshold voltage can only be attributed to sodium contamination introduced during the fabrication of the de-vice. Both the Ce02 and Si02 gate devices were fabricated under the same processing conditions, but the effect of oxide charges was less dramatic in Ce02 than in SiOz' The inter-face charges for both the Ce02 and the SiOz gate MOS de-vices were calculated using the measured threshold voltages. The Si02 gate MOS device yielded an interface charge of 3.8X lOll q C/cm2 with Vr = - 2.4V. With theCeOz gate, the interface charge was 1.5X 1010q C/cm1with VT = O.3V. For the Si02 gate the device is on for zero gate voltage. The normally on effect in the n-type enhancement device using Si02 is a problem that is dealt with by special fabrication methods. Ion implantation is usually required to adjust the J. Vac. Sci. Technol. e, Vol. 9, No.1, Jan/Feb 1991 threshold voltage to positive values. Ce02 does not present this problem and hence does not require an additional pre-cessing step for charge reduction. The transconductance of the device biased at 0.4 rnA is approximately 2 mA/V as obtained from the If) versus Vas curve. This is typical of most MOS devices. 'Y. Nishi()~a, H. Shinriki, and K. Mukai, J. Electrochem. Soc. 136, 872 (1989). "Z. T. AI-Dhhan and C. A Hogarth, Int. J. Electron. 63,573 (1987). JZ. T. AI-Dhhan and C. A. Hogarth, Phys. Status Solidi B 137, k157 ( 1986). 4S. Mochizuki, Phys. Status Solidi B 114, 189 (1982). 'B, Streetman, Solid State Electronic Devices, 2nd ed. (Prentice-Hail, En-glewood Cliffs, NJ, 1990), Chap. 8. 

The Fabrication Of Metal-Oxide Semiconductor Transistors Using Cerium Dioxide As A Gate Oxide Material

A. G. Frangoul

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Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena

The fabrication of metal–oxide–semiconductor transistors using cerium dioxide as a gate oxide material

https://stars.library.ucf.edu/cgi/viewcontent.cgi?article=1228&amp;context=facultybib1990

The Fabrication Of Metal-Oxide Semiconductor Transistors Using Cerium Dioxide As A Gate Oxide Material

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