Model for the quasineutral region capacitance of p/n junction devices

Abstract

The capacitance associated with free-carrier charge storage in the quasineutral region is a primary factor in limiting the switching speed of pin junction devices. This capacitance has been conventionally modeled using assumptions such as low-level injection, nondegeneracy, complete impurity ionization, and no space-charge region thickness modulation. These assumptions can give rise to a large error in device modeling, particularly for modern devices with very small geometry and high bias conditions. In this article, a comprehensive quasineutral region capacitance model including relevant device physics is developed. Comparisons between the present and conventional models are made, and the effects of using these two different models on the total capacitance of junction diode are also investigated