Jensen, Brian Sveistrup

Johansen, Tom K.

Zhurbenko, Vitaliy

Brian Sveistrup Jensen

Tom K. Johansen

Vitaliy Zhurbenko

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A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured in a 0.25 µm SiGe:C BiCMOS technology and its size is 1390 × 2690 µm2. The transmitter demonstrates a maximum output power at 24 GHz of approximately −30 dBm with an externally applied LO power of 3 dBm. The receiver demonstrates a peak gain of 13.3 dB at 22.15 GHz with &gt;10 dB return loss. The power consumption of the entire transceiver is approximately 164 mW

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Downloaded from orbit.dtu.dk on: Dec 19, 2017A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-endJensen, Brian Sveistrup; Johansen, Tom Keinicke; Zhurbenko, VitaliyPublished in:2013 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC)Link to article, DOI:10.1109/IMOC.2013.6646478Publication date:2013Link back to DTU OrbitCitation (APA):Jensen, B. S., Johansen, T. K., & Zhurbenko, V. (2013). A 24 GHz integrated SiGe BiCMOS vital signs detectionradar front-end. In 2013 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC)IEEE. DOI: 10.1109/IMOC.2013.6646478A 24 GHz Integrated SiGe BiCMOS Vital SignsDetection Radar Front-endBrian Sveistrup Jensen†∗, Tom K. Johansen∗, and Vitaliy Zhurbenko∗∗Department of Electrical EngineeringTechnical University of Denmark, 2800 Kgs. Lyngby, DenmarkEmail:tkj@elektro.dtu.dk†Cobham SATCOM2800 Kgs. Lyngby, DenmarkAbstract—In this paper a 24 GHz integrated front-endtransceiver for vital signs detection (VSD) radars is described.The heterodyne radar transceiver integrates LO buffering andquadrature splitting circuits, up- and down-conversion SSBmixers and two cascaded receiver LNA’s. The chip has beenmanufactured in a 0.25 µm SiGe:C BiCMOS technology andits size is 1390 × 2690 µm2. The transmitter demonstrates amaximum output power at 24 GHz of approximately -30 dBmwith an externally applied LO power of 3 dBm. The receiverdemonstrates a peak gain of 13.3 dB at 22.15 GHz with >10 dBreturn loss. The power consumption of the entire transceiver isapproximately 164 mW.I. INTRODUCTIONWireless sensors for the remote detection and monitoringof human vital signs has been of great interest since thefirst sensors were demonstrated in the early 1970’s [1]. Thesensitivity of wireless sensors based on microwave Dopplerradars is limited due to several factors: 1) the large differencebetween the operation wavelength at microwave frequencies(1m to 1 cm) and the much smaller physiological movementsdue to heart and respiration activity, 2) reflections from sta-tionary objects close to the human subject, and 3) interferencefrom random body movements. Furthermore, the received low-frequency baseband signal ranging from 0.1 to 3.3 Hz may beburied in 1/f-noise coming from the electronic components, inparticular the amplifiers and mixers in the receiver chain.For reliable and robust reconstruction of the vital signsa network of sensors operating at high frequency can beexplored. This requires the development of a compact low-cost radar front-end with dedicated single-chip solution. Toovercome some of the limitation experienced with presentVSD radars, which are mainly based on the direct conversion(homodyne) architecture [2], the low-IF heterodyne architec-ture with single-sideband (SSB) transmission was recentlyproposed by the authors [3]. Although the hardware is slightlymore complex, the low-IF heterodyne architecture reduces orcompletely eliminates the problems with 1/f-noise, DC offseterrors, and I/Q channel mismatches. To the best of the author’sknowledge the transceiver front-end presented in this paperrepresents the first integrated vital signs detection radar chipbuilt to demonstrate this concept.The paper is organized as follows. At first, section II givesan overview of the integrated transceiver front-end. Section IIIexplains the sub-circuit designs in details. The experimentalFig. 1. Schematic of the implemented VSD radar front-end IC.results of the chip is presented in section IV. Finally, sectionV concludes the paper.II. CHIP OVERVIEWThe full VSD radar front-end has been designed and man-ufactured as an integrated circuit (IC) in the 0.25 µm SG25H3SiGe:C BiCMOS technology from the German institute ”In-novations for High Performance Microelectronics GmbH”,abbreviated IHP. The technology features five metal layersfrom which the two topmost layers are thicker for improvedimplementation of inductors and microwave structures. Thehigh frequency npn heterojunction bipolar transistor (HBT)available in this technology features ft/fmax = 110/180 GHzwhile having breakdown voltages of 2.3 V.Fig. 1 shows the schematic overview of the implementedIC. It consists of a transmitter chain (Tx) and a receiver chain(Rx) both of which utilize I/Q mixer topologies for SSB opera-tion. The LO signal is split in ±45o branches through a second-order poly-phase filter network and buffers help maintain LOsignal strength all the way to the mixers. An additional inputbuffer has been implemented on the LO port to lower the LOinput power requirements even further. In order to ease testingof the IC, the LO generator is not implemented on-chip. TheIF input (I and Q) are fed from an external source to provide amean for optimizing image rejection (IR) performance throughexternal adjustment of phase- and amplitude balance. At the Txoutput, an external balun is needed to transform the differentialoutput signal into a single-ended signal for the Tx antenna. TheTx output is taken directly following the SSB mixer withoutfurther amplification. This leads to a low transmitted power 978-1-4799-1397-8/13/$31.00 ©2013 IEEECM1CcCcLMTF1Fig. 2. Schematic of transformer-loaded LNA.around -30 dBm. This level, however, was found sufficient dueto the expected short distance to the human subject (typically1-2 m). The Rx chain consists of two cascaded LNA’s designedto provide approximately 27 dB of gain before entering thedown-conversion mixer. The mixer conversion loss has beendesigned to be approximately 14 dB, indicating an expectedtotal receiver gain of approximately 13 dB. Although only oneIF output is needed, both branches of the I/Q mixer is taken outof the chip. When retrieving only one IF output, the expectedreceiver gain thus drops to approximately 10 dB (i.e. 3 dBlower).As indicated in the schematic, the entire chip has beenimplemented using differential designs. This ensures thatcommon-noise rejection and DC offsets are lowered consider-ably; two factors which can be rather high when implementingcircuits on lossy substrates such as Silicon. The only exceptionis the IF input and output branches, which are implementedsingle-ended. However, as shown in the next section, the mixercores are still operating in a differential fashion.III. SUB-CIRCUIT DESIGNSIn this section the design of the sub-circuits in the VSDradar transceiver chip is described.A. Transformer-loaded LNAFig. 2 shows a circuit schematic of the two cascadedLNA’s. The core of each amplifier is based on a cascodebipolar differential pair. The input signal is provided single-ended through the coupling capacitors Cc while CM1 and LMprovide input matching. Biasing of the bipolar pairs Q1/Q2and Q5/Q6 is provided externally through bias resistors RB .The emitter inductors, Le, which are rather small are providedfor a trade-off between gain and bandwidth performance. Thecascode transistors Q3/Q4 and Q7/Q8 are biased directly toV CC through resistors Rs. The bias current for each stage isprovided through a bipolar current mirror which is degeneratedthrough RDEG.Each amplifier is loaded by a transformer with a center tapin one coil for DC biasing. As presented in [4], [5], the use oftransformers have several advantages, as compared to a moretraditional topology using inductors for loading of a singleamplifier. First of all it provides direct AC coupling betweenthe output and the input of the next stage. Furthermore, asthe base input of the HBT (or gate of a MOS) is inherentlyFig. 3. 3D rendering of the transformer simulation setup in Agilent ADS2011.Fig. 4. Schematic of the single-sideband mixer core.capacitive, the secondary coil of the transformer acts as a directmatching component between the output and the input of thenext stage. For precise tuning of the load transformer, thecapacitors CM2 and Cs1/Cs2 are included in the LNA designas shown in Fig. 2.The transformer was optimized separately using electro-magnetic simulations in Agilent ADS 2011. A 3D rendering ofthe transformer simulation setup with center tap on one coil forDC biasing is shown in Fig. 3. The stacking of multiple metallayers was investigated to lower series resistance in the coilsbut was actually found to reduce the quality factor Q due to in-creased capacitive coupling to the substrate. It was also found,that capacitive coupling eliminated the benefit of a patternedground shield often included to minimize the induction of eddycurrents in the substrate. A surrounding ground ring structurewas included in the periphery of the transformer design. Thisground ring allows a better control of the surroundings anda well-defined path for the return current during simulations.The performance of an integrated transformer can be assessedin terms of its so-called Transformer Characteristic Impedance(TCR) which is proportional to the available output power fromthe LNA [4]. An TCR higher than 800 Ω was obtained atthe design frequency of 24 GHz for the optimized structure.This compares well with the 900 Ω reported for the optimizedtransformer structure in [5] at a similar frequency.B. Doubled-balanced single-sideband mixersFig. 4 shows the core of the single-sideband mixer. Itconsists of two identical double-balanced FET resistive ringmixers. Double-balancing is important for isolation betweenFig. 5. Schematic of the LO input buffer, poly-phase filter for 90 degreesplit and LO driver for mixer inputs.different inputs and outputs of the mixer, and ensures thatleakage should be kept at a minimum. The passive FET mixeris incapable of conversion gain but it can be used for both theup- and down-conversion process. This means that the samemixer structure can be used for the transmit and receive path.Using a passive FET resistive topology also reduces 1/f-noisecompared to topologies with a DC biasing current [6]. The1/f-noise in the receiver mixers remains problematic even inthe low-IF heterodyne architecture.As shown in Fig. 4, the RF signal is split between eachmixer. A combined matching is provided through the differ-entially operated inductor LM,RF and the series capacitorsCM,RF . Each of the LO input ports (I and Q) are fed througha similar matching network and combined with a DC biasvoltage through a set of large resistors, RB . This biasing lowersthe requirements to the LO power needed to switch the MOSdevices. The DC current, caused by the biasing will be keptlow through a set of large DC pull-down resistors, RPD, thosepurpose is to ensure a close-to-zero DC voltage on all drainsand sources of the devices. The IF signal from each mixeris taken single-ended with the unused output connected toground.C. LO input buffer with poly-phase filterThe quadrature LO inputs required for the single-sidebandmixers are generated by a second-order poly-phase filtercircuit, [7], as shown in Fig. 5. The externally, providedsingle-ended LO signal is coupled into the circuit through thetransformer, TF1, which makes the LO signal differential. Thesingle-ended matching of the LO inputs is provided throughCM1 and CM2 and is necessary in order to be able to connectthe transformer to ground. CIN provides matching betweenthe transformer and the input buffer consisting of two parallelemitter followers, Q1 and Q2. The capacitors Cc acts as DCblocks such that the emitter followers can be biased throughthe RB resistors.As the poly-phase filter is inherently lossy, LO drivers areneeded to provide the two mixers with an adequate LO signalswing. The LO drivers are implemented as bipolar differentialstages (Q6 and Q7) using double the amount of tail currentFig. 6. Chip photo of the VSD IC fabricated in the IHP SG25H3 SiGe:CBiCMOS technology.Fig. 7. DSB output power as function of LO frequency at an IF drive levelof 26 mVpp at 12 kHz. LO input power was set to 0 dBm.as the input buffers. The bases of the differential pair arebiased directly through the emitter DC voltage of the emitterfollowers and thus do not need an additional bias voltage.Current sources for the entire LO input chain is providedthrough a bipolar current mirror setup using the same reference(Q5). Degeneration resistors, RDEG, are used for higher outputresistance in the current sources. Both the buffer bias voltage,Vbuf,bias, and the current mirror reference supply, Vbuf,cm areexternally fed to the circuit in order to be able to adjust thebiasing when testing the IC.IV. EXPERIMENTAL RESULTSFig. 6 shows a photo of the manufactured VSD chipwith the different circuit blocks marked by rectangles andlabels. The dimensions of the IC is 1390 × 2690 µm2. Thechip has been measured on-wafer and consumes a power ofapproximately 164 mW.At first the transmitter block has been tested using anAnritsu MG3694A 40 GHz signal generator for the LO inputand a TTi TG120 20 MHz function generator for the IFinput. The RF output power has been measured on an HP8563E spectrum analyzer taking into account all losses relatedto cables and interconnects. Throughout the testing the IFfrequency was set to 12 kHz. Fig. 7 shows the measuredoutput power including both sidebands from the transmitterusing a 0.26 mVpp IF signal and 0 dBm LO power. As seen,the transmitter has a center frequency of approximately 24GHz as intended. However, the output power is approximately5 dB lower than simulations. The reason for this could be anunderestimation of the losses in the critical matching inductorsof the mixer and a lowering of the LO drive level providedby the LO buffer network. The output power as a functionFig. 8. DSB output power as function of LO input power at 23 GHz withall other parameters constant.Fig. 9. Reflection measurements versus frequency at the receiver input.of LO input power at 23 GHz is shown in Fig. 8. A largedifference between measured and simulated output power isobserved especially at lower LO input power levels. Thisindicates that the model employed for the passive MOS devicesin the switching quad is inaccurate in the quasi-linear region.It is also observed that the LO buffer network is not fullysaturated at 0 dBm LO power which may explain part of theobserved difference in Fig. 7. At the maximum drive level (10dBm) provided by the Anritsu RF generator, the output poweris approximately -30 dBm. The image rejection was tested at1 kHz where an IF quadrature splitter was available and gavean suppression of the unwanted sideband of more than 40 dB.This shows that the IC with the correct IF circuitry can beconfigured to function as a single-sideband transmitter.The return loss of the receiver, as shown in Fig. 9, hasbeen measured on an Anritsu ME7808B VNA. Although com-parison to simulation reveals a small down-shift in frequencyand a poorer match, the return loss remains better than 10dB for the band between 18 and 24 GHz. This is acceptablefor the targeted application. The down-conversion operation ofthe receiver has been measured in a loop back test, where theoutput of the transmitter has been connected to the input ofthe receiver. Fig. 10 shows the measurement of the receivergain when the variations in the transmit power has beencompensated for. It is seen that the receiver is shifted slightlydown in frequency, with a peak gain of 13.3 dB at around22.15 GHz. Nonetheless, the receiver produces sufficient gainthrough the down-conversion process and it can be concludedthat the chip seems usable in a VSD system.V. CONCLUSIONA 24 GHz SiGe BiCMOS VSD radar front-end chiphas been presented. The chip integrates a low-IF heterodyneradar transceiver and can be configured for single-sidebandtransmission by providing IF signals in quadrature phase. Thechip is designed for a high carrier frequency of 24 GHzFig. 10. Receiver gain measurements performed with a loop-back test of thetransmit signal.potentially reducing size and increasing the sensitivity of futureVSD sensor networks.ACKNOWLEDGMENTThe authors would like to thank the Danish fund, H. C.Ørsteds Fonden, for financial support.REFERENCES[1] J. C. Lin, ”Microwave Movement Sensing of Physiological and VolumeChange: A Review,” Bioelectromagnetics, vol. 13, No. 6, pp. 557-565,1992.[2] A. Droitcour et al., ”Range Correlation and I/Q Performance Benefitsin Single-Chip Silicon Doppler Radars for Noncontact CardiopulmonaryMonitoring,” IEEE Trans. Microwave Theory and Tech., vol. 52, No. 3,pp. 838-848, March 2004.[3] B. S. Jensen, S. P. Jonasson, T. K. Johansen, and T. Jensen, ”Vital signsdetection radar using low intermediate-frequency architecture and single-sideband transmission,” in Proc. 9th European Radar Conference, pp.67-70, Amsterdam, The Netherlands, Nov., 2012.[4] F. Carrara et al., ”Design Methodology for the Optimization ofTransformer-Loaded RF Circuits,” IEEE Trans. Circuits and Systems,vol. 53, pp. 761-768, April 2006.[5] V. Ragonese et al., ”A SiGe BiCMOS 24-GHz Transceiver Front-end forAutomotive Short-Range Radar,” Analog Integrated Circuits and SignalProcessing, vol. 67, pp. 121-130, Oct. 2011.[6] C. Song et al.,”0.18-µm CMOS Wideband Passive Mixer”, Microwaveand Optical Tech. Letters, vol. 55, no.1, Jan. 2013.[7] J. Kaukovuori et al., ”Analysis and Design of Passive Polyphase Filters,”IEEE Trans. Circuits and Systems, vol. 55, pp. 3023-3037, Nov. 2008.

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A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

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