Ieda, Nobuaki

Murota, Junichi

Ohmori, Yasuo

Tanimoto, Masafumi

IEEE Transactions on Electron Devices

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Tohoku University Repository (TOUR) / 東北大学機関リポジトリ

A Novel MOS PROM Using a Highly ResistivePoly-Si Resistor著者 室田  淳一journal orpublication titleIEEE Transactions on Electron Devicesvolume 27number 3page range 517-520year 1980URL http://hdl.handle.net/10097/47740IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 3, MARCH 1980 5 1 1  A Novel MOS PROM Using a Highly Resistive Poly-Si Resistor MASAFUMI TANIMOTO, JUNICHI MUROTA, YASUO OHMORI, AND NOBUAKI IEDA 0018-9383/80/0300-0517$00.75 0 1980 IEEE Abstract- A novel MOS electrically  programmable  read-only  memory (PROM) using a highly resistive polycrystalline  silicon @olySi) resistor as a memory  element is proposed. In a  highly  resistive  poly-Si,  a  new memory  effect of an  irreversible resistivity transition, from an initial highly resistive value to a iow- resistive one, is observed. The dependencies of the transition voltage and current, which  cause the transition, on the poly-Si deposition conditions, are studied, and the deposition conditions suitable for MOS  PROM fabrication are obtained. The transition voltage Vt  can be reduced  down to 10 V by decreasing the  polySi film  thickness to 0.4 pm.  The  transition  current is less  than 10 mA. A 36-bit MOS PROM, using the poly-Si resistor  as a memory  element, is fabricated.  The  programming  voltage used in this work is 25 V and the programming  time  per bit is less  than 10 ps. The  read access time is less than  300 ns. The  programming voltage,  however, can be reduced down to 15 V by decreasing the poly-Si film thickness  and  the series resistance in the circuit. The novel PROM has another advantage in that  the poly-Si resistor is compatible  with a conventional siliconsate process. I. INTRODUCTION A READ-ONLY MEMORY  (ROM)  is  an important device for code conversion, character generation, and micro- programming. Various types of ROM’s have been developed [I]  -[7] . Among these ROM’s, an electrically programmable ROM (PROM) is remarkably superior to a mask ROM in a small-volume memory system. Moreover, MOS PROM’s have an advantage over bipolar PROM’s in chip cost. There are two types of MOS PROM’s. One is an alterable PROM. Since alterable PROM’s can  be  erased by  applying voltage or by exposing to ultraviolet light, they can be pro- grammed over and over again. They require, however, a high programming voltage, and some of them, such as MNOS, re- quire a very thin gate  oxide  which is not used in MOS random- access memory.  The  other is a fusable-link PROM. The programmed state of the fusable-link PROM is stabler than that  of  the alterable PROM  because the  programming is carried out  by blowing a fusable-link instead of storing charges into a floating gate or a trapping state. However, this PROM also requires a high  programming  voltage to flow a large program- ming  current. In this paper, a novel MOS PROM using a polycrystalline silicon (poly-Si) resistor as a  memory  element is proposed.  A poly-Si resistor is composed of highly resistive poly-Si  whose resistivity is above lo3 SZ cm. An irreversible resistivity Manuscript  received March 8, 1978;revised August 8,1979. The authors are with Musashino Electrical Communication Labora- tory,  Nippon Telegaph and Telephone  Public  Corporation, Musashino- shi, Tokyo, 180 Japan. HIOHLY-RESISTIVE WLY-SI i Aluminium Fig. 1. Cross-sectional view of the highly  resistive  poly-Si resistor. transition in highly resistive poly-Si is used for programming the PROM. This PROM is a kind of the fusable-link PROM. The voltage and current required for this transition can be reduced down to 10 V and less than 10 mA, respectively. Therefore,  the  programming voltage and  current  of  the PROM are small, compared with those of other MOS PROM’s. The fabrication process of the PROM requires no special tech- nology because the poly-Si resistor is fabricated  by a conven- tional silicon-gate process. Section I1 describes some experimental results for the irre- versible resistivity transition in polySi. The  deposition  condi- tion of poly-Si, which is applicable to a memory element of MOS  PROM,  is also given. Section 111 covers  the PROM fabri- cation and experimental results obtained  from  the PROM. Section  IV  summarizes  the results of this work. 11. MEMORY EFFECT IN HIGHLY  RESISTIVE POLY-Si A .  Sample Preparation The fabrication process of the poly-Si resistor, shown in Fig. 1, is  as follows. First, a highly arsenicdoped poly-Si, whose resistivity is below 2 X lo-* S2 cm, is deposited on n-type, (IOO), 1.5-8 - cm substrate as a lower electrode. Then, a highly resistive poly-Si, whose resistivity is  higher than 1 X lo3 SZ - cm, is deposited, by pyrolysis of SiH4-H2- AsH3 system, in an RF-heated  horizontal  reactor  at-tempera- tures between 650 and 750°C. An upper electrode is com- posed of  highly  arsenic-doped poly-Si, whose resistivity is about 2 X SZ cm, and  aluminum  etallization  on top of the polySi electrode. CVD SiOz is used to insulate the highly resistive poly-Si from each electrode, except for the active region,  and  the  current path is constructed  perpendicu- lar to the  substrate, as shown in Fig. 1 .  ___ - . -. .~.  .- B. Current- Voltage Characteristics Typical  current-voltage characteristics of the  polySi resistor are shown in Fig. 2. In the initial highly resistive state, the current is proportional to the voltage in a low  applied voltage region, Though the current becomes unproportional to the Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on March 03,2010 at 03:01:56 EST from IEEE Xplore.  Restrictions apply. 518 IEEE TRANSACTIONS ON ELECTRON DEVICES, VQC. ED-27, NO. 3, MARCH lyou h Y a I- @ a Id6  CONDUCTIVE STATE 0. I I IO VOLTAGE ( V I  Fig. 2. Current-voltage  characteristics of the polySi resistor. voltage in a high applied voltage region,-the current-voltage characteristic is reversible. When the applied voltage exceeds the transition voltage V,, the highly resistive polySi resistor is changed irreversibly into a low-resistive one. In this low- resistive state,  the current-voltage characteristic of  the  polySi resistor is linear over  all the voltage  region  even  when a reverse bias is applied. The  current  path in this low-resistive polySi is observed by the  following  procedure. An aluminum  metallization  layer, an upper poly-Si electrode,  and  an  upper  SiOz  film are removed by chemical etching. The highly resistive polySi film is Sirtl etched slightly. A selective etched area of about 1-pm diam- eter is observed. This means that the structure of polySi is changed locally. Therefore,  it is suggested that 1) the  current concentrates in a small area in the low-resistive polySi, and 2) the irreversible resistivity transition of  the  polySi resistor is  caused by  the  structural change of  highly resistive polySi. A similar memory  effect is obtained  for  a variety of  sample structures. For  example, it is obtained  with  a  sample in which the lower and upper electrodes are made of an nf-diffgs& layer  and^ an iiumiiiim (or molybdenum)  metallization  layer, respectively. It is also obtained with a sample in which the positions of the upper and lower electrodes are separated in parallel to  the  substrate, and the current path is constructed obliquely to  the  substrate. In this work, arsenic-doped polySi is chosen as an upper electrode  and the distance  between the electrodes is controlled by  the film thickness in order to obtain  the  uniformity  of  the transition voltage within a lot and for different lots. This memory element using the poly-Si resistor is expected to be compatible  with  a  conventional MOS process. C. Dependence of Transition Voltage V, on Deposition Condition , . . -. . - ~~ .~ .- . . To realize a memory device with the polySi resistor, it is indispensable to lower the transition voltage V,. The relation- ships between the  transition voltage and  deposition  conditions, DEPOSITION TEMPERATURE CC) Fig. 3. Deposition temperature dependence of transition voltage Vt. o . ~  a4 0.6 ID 2.0 FILM THICKNESS ( pm) Fig. 4 .  Film thickness dependence of transition voltage V,. Fig. 5 .  Initial  resistivity dependence of transition  voltage V,. such as deposition temperature, film thickness, and partial pressure  of AsH3 , are studied. Fig. 3 shows  the  deposition  temperature  dependence  of  the transition voltage for an  undoped  polySi  of 1 -0-pm thickness. The transition voltage decreases abruptly above 70doC. The preferred orientation of the polySi film changes from the random  orientation to the (1 10) orientation when the  deposi- tion temperature is above 70OoC. It is considered that the transition voltage depends on  the  structure  of  the  polySi film. To make  the  transition  voltage variation small with  the deposi- tion  temperatuire,  the  deposition  temperature  should  be  below 700°C. Fig. 4 shows the film  thickness  dependence  of  the transition voltage for an undoped poly-Si deposited at 70OoC. The  tran- sition voltage is proportional to  the film thickness. The elec- tric field in the film is approximately 2 X lo5 V/cm. It is possible to obtain a transition voltage of less than 10 V by decreasing the film thickness down to 0.4pm, as shown in Fig. 4. Fig. 5 shows  the initial resistivity dependence  of  the transi- tion voltage for the highly resistive polySi with a 1.0-pm thickness, deposited at 700°C. The initial resistivity is vaned from 1 X lo3 to 1 X 10' Ci - cm by varying the AsH3 partial pressure  during  deposition  of  the polySi. The transition voltage  tends to increase with  the initial resistivity. The transi- .__. -.-. Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on March 03,2010 at 03:01:56 EST from IEEE Xplore.  Restrictions apply. TANIMOTO et al.: NOVEL MOS PROM 519 BIT LINE ? Fig. 6. Microphotograph of the MOS PROM. Effective area is 0.7 mm X 0.7 mm. HIGHLY-RESISTIVE POLY-SI ARSENIC-DOPED POLY-SI / Alumlnlum tion  voltage can be  made less than 10 V by lowering the initial resistivity down to 1 X lo4 51 * cm, even for a 1 .O-pm film thickness. Undoped polySi, however, is preferable because it is difficult to control the initial resistivity by varying the AsH3 partial pressure. D. Application to Memory Element in PROM As described  above,  the  poly-Si resistor has  a  memory  effect and  its  transition voltage is low.  The pulsewidth dependence of the transition voltage V, is small; for  example, V;’S at 0.1-ps pulsewidth  and at 1.0 ps are larger than  that  under  dc  con&- tion  by only 15 and 5 percent, respectively. The  current required for the irreversible transition (transition current I,)  depends on deposition conditions, electrode area, and film thickness. The transition current is from 1 to 10 mA, when the transition voltage is from 2 5  to 10 V and the electrode area is below 100 pm2. The total deviations  from  the average value of the transition voltage V, and  current It for different lots are 10 percent for V, and 30  percent  for It. The  stability of the  polySi resistor in low: and highly  resis- tive state is tested  at 100°C with an applied voltage of 10 V. The resistance of the poly-Si resistor does not change under these  conditions. The  ratio of the resistance in a  highly resistive state to  that in a low-resistive state is  larger than lo4 in a low applied voltage  region at  emperatures below 70°C. The  tempera- ture dependence  of  the transition voltage Vt is small; for example, Vt at 70°C is only 10 percent smaller than V, at room  temperature. From these results, it is confirmed that  the  polySi resistor will become  an  excellent  memory  element  of an  MOS  PROM. 111. MOS PROM . ... ~. A. Fabrication A  36-bit MOS  PROM  using the  poly-Si resistor is fabricated. Its microphotograph is shown in Fig. 6. The PROM is con- structed  with  a  6 X 6  bit  memory cell array,  address selecting MOSFET’s, and an output amplifier. Fig. 7(a) and (b) shows an equivalent circuit and a cross-sectional view of a memory cell, respectively. The cell consists of  a polySi resistor and  a selecting MOSFET, which are connected in series. A conventional  n-channel silicon-gate process  is  used to fabricate this device on a p-type, (loo), 1.5-51 cm substrate. The MOSFET has a gate oxide thickness of 1000 a and an (b) Fig. 7 .  Memory cell. (a) Circuit diagram. (b) Cross-sectional view. I I I t+v I I BIT LINE I I I I  I !  b w 5  Fig. 8. Circuit  diagram of the MOS PROM. effective channel  length  of 5 pm. The threshold voltage of  the MOSFET is 1.1 V when the substrate bias voltage is -2  V. The poly-Si resistor, as shown in Fig. 1, is constructed with undoped polySi  on  the n+-diffused drain region of  the  FET. Undoped poly-Si is deposited at 700°C. The film thickness of poly-Si  is selected as 0.6  pm because the transition voltage should be larger than the power supply voltage VDD of the PROM. The transition voltage of this film is expected to be 15 V, while VDD is 10 V. B. Device Operation A circuit diagram of the PROM is shown in Fig. 8. The programming operation can be performed as follows. A cell (Xi, 5) is selected by raising the X~ELECT i and Y ~ E L E C T ~  line Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on March 03,2010 at 03:01:56 EST from IEEE Xplore.  Restrictions apply. 520 IE,EE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 3, WA?.C-T ? PT?? Fig. 9.  Operation waveforms. potentials and a voltage larger than the transition voltage is applied to the VPROG. The resistance of a highly resistive poly-Si resistor is lowered and  the programming operation is accomplished at this particular address location. Read operation can be  performed in the following manner.  The bit line is precharged through a transistor Ql by the msignal.  A cell (Xi, q) is selected by raising the XSELECT~ and YSELECT~ line potentials. As a result, the potential of the precharged bit line decreases. The  time  constant of this transient response is determined by the resistance of a highly resistive polySi resistor, g,, of the MOSFET, and parasitic capacitance. Since the ratio of the resistance for the poly-Si resistor in a highly resistive state to that  in a low-resistive state is about lo4, the time constant difference between “1” and “0” written in a cell  is  very large. Therefore, the information in a selected cell can be read by monitoring the bit-line voltage by the source-follower transistor Q,  . The programming  and  read operations  of the fabricated PROM are successfully verified. The programming  voltage is 25 V and  time required for programming is less than 10 ps per bit. Read access is less then 300 ns. Output waveforms of this PROM, when  stored  information “1” and “0” are read, are shown in Fig. 9. The resistor of 5 ks1 is connected to the VouT.  The following voltages are used to operate  this PROM: PROGRAMMING: Vx,y SELECT = 20 V VPROG = 25 V READ : VX,Y SELECT = 10 V CE= 10 v. - In the programming mode, VX,YSELECT is chosen to be 20 V to provide the  current required for  the programming. On the other hand, V~,YSELECT is chosen to be 10 V in the read mode. A dc bias voltage of 10 V is applied as V& and that of  -2 V as the substrate bias VBB.  In this fabricated PROM  using 0.6-pm-thick poly-Si, the  pro- gramming  voltage  is expected to be 20 V, taking into account the potential drops in the address selecting transistors. How- ever, the programming voltage VPROG  used in this work is 25 V, because of potential  drops in the  upper poly-Si electrode and common line which is connected in series to the highly resjstive polySi resistor. The resistance of  an  upper  electrode is more  than 500 s1 because it is composed  of  an arsenic-doped polySi whose  resistivity  is about 2 X lo-, s1 * cm as described in Section 11-A. The common line, connecting memory cell and Y-select transistor, is  composed  of a diffused layer ~dm: sheet resistance is about 15 s2/0. The total resistance of t I L e  common line is, for example, about 1 kS2 for rrlernory ce:,il (X,, Yl). The potential drops in the upper poly-Si c:lect:cxle and the  common line can be reduced by optimizing 1x1:I sl.ruc- ture  and physical layout.  Therefore, VPROG can be lowered t o  20 V. Moreover , VPROG can be reduced down to 15 7 J  s:im; the transition voltage is expected to be 10 V by decreasing . t h e  poly-Si film thickness to 0.4 pm. IV. CONCLUSIONS A memory effect in a highly resistive polySi and a novel MOS  PROM  using this memory effect are described. An irreversible transition  from a highly resistive slate to a low-resistive state is observed in a highly resistive .po’ly-Si. The  transition voltage V, at which the highly resistive pol:y.’Si resistor is  changed to a low-resistive one can be reduced down to 10 V by increasing the  deposition  temperature  and  by decreasing the film thickness and the initial resistivity. The current necessary for  this  transition is  less than 10 mA. A 36-bit MOS  PKOM,  using the poZySi resistor as a menwry element, is fabricated. This novel  PROM has an  aclva.ntage in th.at it can be programmed with a low voltage aad a small current.  In  addition,  its  fabrication process requires no splxial technology, because the poly-Si resistor is fabrimted by a conventional silicon-gate process. ACKNOWLEDGMENT The  authors wish to thank  Dr. H. Toyoda,  Dr. H. Yoshimura, M. Kondo,  and M. Hirai, for their support of this work:, and Dr. T. Asaoka for his useful discussions and  comments.  They are also grateful to their colleagues at  he  Semiconductor Memory Technology Section, and Mask and Pattern Genera- tion  Section  for the device fabrication. REFERENCES [ 11 D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, pp. 1288-1295, [2] D. Frohmann-Bentchkowsky, “A fully-decoded  2048-bit  elec.trically- programmable MOS  ROM,” in ISSCC Dig.  Tech.  Papers, pp. 80-81, Feb. 1971. [ 31 J. T. Wallmark and J. H. Scott, “Switching and storage character- istics of MIS memory transistors,” RCA Rev. ,  vol. 30, PIP. 335- 365, June 1969. [4] Y. Uchida, N. Endo, S. Saito, M. Konaka, I. Nojima, Y. Nishi, and K. Tamaru, “A 1024-bit MNOS RAM using avalanche-tunnel in- jection,” in ISSCCDig.  Tech.  Papers, pp. 108-109,  Feb.  1975. [SI J. Scharbert and  H.  Murrmann, “A 1024-bit ECL-PROM with 15ns access,” in ISSCCDig.  Tech.  Papers, pp.  106-107,  Feb.  1975. [6] T. J .  Rodgers, R. Hiltpold, J. W. Zimmer, 6. Marr, and J. D. Trotter, “VMOS ROM,” IEEE J. Solid-state  Circuits, vol. SC-11, [7] J. E. Schroder and R. L. Gosline, “A 1024-bit fused-link CMOS PROM,” in ISSCCDig.  Tech.  Papers, pp.  190-191,Feb. 1917. July-Aug. 1967. pp. 614-622, Oct.  1976. Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on March 03,2010 at 03:01:56 EST from IEEE Xplore.  Restrictions apply. 

A Novel MOS PROM Using a Highly Resistive Poly-Si Resistor

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A Novel MOS PROM Using a Highly Resistive Poly-Si Resistor

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