An influence of the selected physical phenomena: impact ionization in silicon and time variation of internal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the socalled „pinch-off” region is discussed in a more detailed way. The analysis is done using a numerical solver of drift-diffusion equations in silicon devices and using an analytical model of the PD SOI MOSFETs. The calculations results exhibit the significance of proper modelling of the phenomena in the floating body area of these devices

Gibki, Jan

Jakubowski, Andrzej

Tomaszewski, Daniel

Łukasiak, Lidia

Biblioteka Cyfrowa Instytutu Łączności / National Institute of Telecomunications: Digital Library

Paper An impact of physicalphenomena on admittancesof partially-depleted SOI MOSFETsDaniel Tomaszewski, Lidia Łukasiak, Jan Gibki, and Andrzej JakubowskiAbstract — An influence of the selected physical phenom-ena: impact ionization in silicon and time variation of inter-nal electric field distribution in partially-depleted (PD) SOIMOSFETs on several C-V characteristics of these devices ispresented. The role of avalanche multiplication in the so-called „pinch-off” region is discussed in a more detailed way.The analysis is done using a numerical solver of drift-diffusionequations in silicon devices and using an analytical model ofthe PD SOI MOSFETs. The calculations results exhibit thesignificance of proper modelling of the phenomena in the float-ing body area of these devices.Keywords — SOI MOSFET, floating body, avalanche ionization,recombination, displacement current, admittance.1. IntroductionIt is well known, that I-V characteristics of partially de-pleted silicon-on-insulator (PD SOI) MOSFETs are deter-mined by the balance of internal current components, whichoriginate from different phenomena in intrinsic and extrin-sic parts of the device. This was confirmed in several worksand by numerical simulations. Obviously the same phe-nomena influence the C-V characteristics of the PD SOIMOSFETs [1, 2]. Due to the strong impact of these phe-nomena on the AC data reliable small-signal models of thePD SOI MOSFETs are relevant for the characterization anddesign purposes.Below brief discussion of the influence of several phenom-ena on PD SOI MOSFETs capacitances is presented. It isbased on preliminary numerical simulations and on com-putations made using an analytical small-signal non-quasi-static model of the PD SOI MOSFETs.2. Numerical analysis of the PD SOIMOSFETs capacitancesNumerical simulation is a very valuable tool for detailed in-vestigation of physical phenomena, which determine elec-trical characteristics of the semiconductor devices. Oneof the main advantages of this approach is a possibilityof selective turning on/off the models of the particular phe-nomena. Owing to this an engineer may compare electricalcharacteristics of the device obtained with or without ac-counting for the given mechanism. Such approach is notpossible when experimental data are analysed.Impact ionization is very important for determining elec-trical parameters of the PD SOI MOSFETs. A role ofimpact ionization for I-V and C-V characteristics becomesmore clear using the approach mentioned above. Figure 1shows comparison of Cg f s(VDS) and Cg f d(VDS) data of thePD SOI MOSFET, calculated using ATLAS/SPISCES pro-gram [3] with avalanche ionization turned on and turnedoff. Parameters of the simulated device are as follows:L = 0.6 m m, tSi  0:2 m m, tox;b  0:4 m m, tox; f  30 nm,NB  5 1016 cm 3.Fig. 1. Influence of the impact ionization in silicon on the frontgate-to-source and front gate-to-drain capacitances of the PD SOIMOSFET obtained with numerical simulations [3]. Comparisonhas been done by switching on/off the impact ionization compo-nents in the drift-diffusion equations. The device parameters arementioned in the text.For impact ionization turned on the following effects maybe distinguished, which may be observed neither in bulkMOSFETs nor in hypothetic PD SOI MOSFETs withoutavalanche multiplication: increase of the Cg f s capacitance in saturation rangefor increasing VDS voltage; decrease of the Cg f d capacitance in saturation almostbelow zero farads for increasing VDS voltage.Of course Cg f s and Cg f d capacitances consist of intrinsicand extrinsic components [4]. Extrinsic parts are related57Daniel Tomaszewski, Lidia Łukasiak, Jan Gibki, and Andrzej Jakubowskito overlap and fringing capacitances and are almost con-stant. Intrinsic parts result from variation of electric fieldbelow the gate. If extrinsic components were „subtracted”from the total Cg f d(VDS) curve, then it would appear, thatintrinsic component of Cg f d capacitance became negative.This result is not possible in the conventional MOSFETs,where Cg f d capacitances approaches zero farads in satura-tion range. Moreover Flandre estimated in [1], that a small„plateau” visible in Cg f s data (1 V  2 V, depending on theVG f S value) corresponded to Cg f s value of ca. 0:72 Cox; f ,where Cox; f denotes front gate voltage of the device anal-ysed in [1]. Therefore it would considerably exceed valueof 2=3 Cox; f , which is typical for bulk transistors. All theeffects mentioned above are strictly related to the avalancheionization in the depletion area of the drain-body junction.It is also worthwile to mention, that Cg f s(VDS) character-istics of the PD SOI MOSFETs calculated with ionizationturned off, differ from the same data obtained for the con-ventional MOSFETs. A VG f S–controlled variation of theCg f s value in the saturation range can be observed only inthe hypothetic PD SOI MOSFETs. This effect is probablydue to small variations of the body potential, even if a largenumber of excess holes generated by ionization do not en-ter the thin Si-film. This may induce appropriate change ofwidth of front gate depletion area and finally a change ofCg f s intrinsic component related to coupling between frontgate and source through the „pinch-off” region.The simulator does not allow to switch multiplication on/offselectively, so the characteristics in Fig. 1 reflect the overalleffect of the impact ionization in the space-charge regions,surrounding drain-body junction, where high electric fieldexists. However ionization in the „pinch-off” region is par-ticularly relevant, because number of holes generated thereand injected into the floating, quasi-neutral body area is sev-eral orders of magnitude higher, than the number of holesgenerated in the depletion region of the drain body junction.This results from the fact, that drift current component atthe interface is much more higher, than the parasitic currentflowing in the bulk part of the Si-film.3. Role of displacement currents at thesource-body and drain-body junctionsDisplacement current components flowing through the ex-trinsic gate-source and gate-drain capacitances (for bothgates) are connected in-parallel with the appropriate intrin-sic capacitances. As has been mentioned earlier, they arealmost constant, so their effect is self-evident. They simplyincrease the total capacitances. Moreover, as the currentsflowing through them are purely capacitative, they do notinfluence the character of intrinsic admittances, i.e. they donot modify their partitioning between capacitance and con-ductance. Therefore for the simplicity it has been assumedhere, that gates fringing capacitances may be neglected.Further brief analysis will be concerned with displacementcurrents at the junctions.Figures 2 and 3 show fragments of Cg f s(VG f S) andCg f d(VDS) characteristics of the PD SOI MOSFET, obtainedusing the model [5]. They were calculated for the deviceparameters, which are given in [6, Table 1]. Data pre-sented in Fig. 2 correspond mainly to the accumulationrange and transition between weak and strong inversion,which however is not modelled properly (in this model ver-sion subthreshold range is not accounted for). Data shownin Fig. 3 correspond to transition between non-saturationand saturation ranges.Fig. 2. The influence of the displacement current at the source-body junction for the Cg f s capacitances in the accumulation range.Fig. 3. The effect of the displacement current at the drain-bodyjunction for the Cg f d capacitances in the saturation range.In the accumulation range neglecting of the S-B junctiondisplacement current causes, that Cg f s capacitance van-ishes. It means, that in this way the only path (except ofneglected fringing capacitance) for HF signal propagationfrom source to front gate becomes closed. Thus in accu-mulation S-B junction admittance is connected in parallelwith other components of the front gate-source admittance.Figure 2 illustrates also decrease of the junction admittancefor increasing front gate voltage. It is caused probably bythe narrowing of the quasi-neutral part of the Si-film, asfront-gate induced depletion region widens.In the saturation range (Fig. 3) Cg f d capacitance calculatedusing the model [5] is also determined by parasitic compo-58An impact of physical phenomena on admittances of partially-depleted SOI MOSFETsnents related to fringing capacitances (neglected) and ad-mittance of the drain-body junction. As expected in caseof neglecting of displacement current component flowingthrough this junction Cg f d vanishes to zero farads. Howeverfor sufficiently large drain-source voltage and gate-sourcevoltage equal 2 V decrease of Cg f d below zero may be ob-served. For VG f S = 4 V saturation and „kink” ranges areshifted towards higher values of VDS, so effect of impactionization on Cg f d capacitance is not visible. Brief discus-sion of this effect based on results of numerical compu-tations was presented in the previous section. Its analysisbased on computations made using the analytical model ispresented in the next section.4. Role of phenomena in the „pinch-off”regionIn the saturation range Cg f d capacitance calculated usingthe model [5] is determined by parasitic components re-lated to fringing capacitances (neglected) and admittanceof the drain-body junction. This is analogous to the caseof conventional MOSFETs. However contrary to bulk de-vices the D-B junction admittance has not purely capaci-tative character. In the drain bias range beyond „kink” itbehaves rather like RLC circuit [7]. As a result, currentcomponents flowing through areas of high electric field in-duce such phase shift between AC components of the drainvoltage and body potential, that intrinsic component of Cg f dcapacitance becomes negative. Figure 4 illustrates this ef-fect. However turning off the appropriate AC componentFig. 4. The influence of the impact ionization in the „pinch-off”region upon the Cg f d capacitances in the saturation range. Thesedata are consistent with Fig. 1.of the drain current does not remove it completely. Soa conclusion may be done, that a generally valid balanceof all the AC currents in the PD SOI MOSFET makes, thattheir capacitances differ significantly from the appropriatecapacitances of the bulk devices. Even a small differencein phases or amplitudes of currents AC components mayinduce unusual admittance behaviour.Fig. 5. The influence of the impact ionization in the „pinch-off”region upon the Csd capacitances in the saturation range.Fig. 6. The influence of the impact ionization in the „pinch-off”region upon the Cds capacitances in the saturation range. Thenonreciprocality of the Cds and Csd capacitances is obvious.Figures 5 and 6 show also effect of impact ionization onCds and Csd capacitances of the PD SOI MOSFET. It isvery difficult to measure these variables, because during themeasurement a large current flows between source and draincontacts. Such data are not available in the literature. Onlysimulated characteristics may be compared and discussed.The data presented in Figs. 5 and 6 show that in the satu-ration range switching the impact ionization off completelychanges character of these capacitances. More detailedanalysis of this effect is very difficult and will be presentedin future together with comparison with characteristics ob-tained numerically. The eventual improvement of the modeltowards better modelling high-frequencies effects should bealso considered. These data in Figs. 5 and 6 also illustrate,that both capacitances are non-reciprocal, which is typicalfor multi-port active devices.5. ConclusionsThe small-signal model of the PD SOI MOSFETs showsqualitatively the importance of the following phenomenafor the proper modelling of C-V characteristics:59Daniel Tomaszewski, Lidia Łukasiak, Jan Gibki, and Andrzej Jakubowski displacement current at the source-body and drain-body junctions, avalanche multiplication of carriers within the„pinch-off” region.Moreover it may be stated, that generation/recombinationphenomena are less critical for the small-signal analysis ofthese devices.AcknowledgmentThe work was supported by the State Committee of Scien-tific Research under grant no. 8T11B 04 017.References[1] D. Flandre, „Analysis of floating substrate effects on the intrinsicgate capacitance of SOI MOSFET’s using two-dimensional devicesimulation”, IEEE Trans. Electron Dev., vol. 40, no. 10, pp. 1789–1796, 1993.[2] S. Cristoloveanu and S. S. Li, Electrical Characterization of Silicon-on-Insulator Materials and Devices. Kluwer Academic Publishers,1995.[3] SILVACO, ATLAS User’s Manual, Ver. 4.0, June 1995.[4] C. H. Wang, „Identification and measurement of scaling-dependentparasitic capacitances of small-geometry MOSFET’s”, IEEE Trans.Electron Dev., vol. 43, no. 6, pp. 965–972, 1996.[5] D. Tomaszewski, J. Gibki, A. Jakubowski, and M. Jurczak, „A small-signal non-quasistatic model of partially depleted SOI MOSFETs”, inProc. Ninth Int. Workshop Phys. Semicond. Dev., Delhi, Dec. 16–20,1997, pp. 1076–1079.[6] D. Tomaszewski, L. Łukasiak, A. Zaręba, and A. Jakubowski, „Animpact of frequency on capacitances of partially-depleted SOI MOS-FETs”, J. Telecommun. Inform. Technol., no. 3/4, 2000.[7] W. T. Read, „A proposed high frequency negative resistance diode”,Bell Syst. Techn. J., vol. 37, pp. 441–446, 1958.Jan Gibki received the M.Sc. degree in electronics fromthe Warsaw University of Technology in 1974 and the Ph.D.from Institute of the Electron Technology in 1997. From1976 to 1982 he was working for the Military Academyas an assistant lecturer. From 1986 to 1989 he was in-volved in the development of methods for MOS transistorsmodels parameters extraction in the Institute of ElectronTechnology, Warsaw. Since 1998 he has been working forthe Institute of Microelectronics and Optoelectronics at theWarsaw University of Technology. Currently, his main re-search interest is in developing method of the SOI deviceand technology characterization. He is the author or co-author of about 40 technical papers and communications atconferences.e-mail: gibki@imio.pw.edu.plInstitute of Microelectronics and OptoelectronicsWarsaw University of TechnologyKoszykowa st 7500-662 Warsaw, PolandAndrzej Jakubowski – for biography, see this issue, p. 33.Lidia Łukasiak – for biography, see this issue, p. 34.Daniel Tomaszewski – for biography, see this issue, p. 39.60

An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs, Journal of Telecommunications and Information Technology, 2001, nr 1

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An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs, Journal of Telecommunications and Information Technology, 2001, nr 1

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