Implementation of RISC Processor for DSPAcceleratorArchitectureExploiting Carry Save Arithmetic

Abstract

Hardware acceleration has been proved an extremely promisingimplementation strategyforthedigitalsignal processing(DSP) domain.Ratherthanadoptingamonolithicapplication-specificintegrated circuit designapproach,  in thisbrief, we present a  novel accelerator architecture comprising flexiblecomputational  units that support the executionofalargesetofoperationtemplatesfoundinDSPkernels. Wedifferentiatefrompreviousworksonflexibleacceleratorsbyenabling computations tobeaggressivelyperformedwithcarry-save(CS)formatteddata.Advancedarithmeticdesignconcepts, i.e.,recodingtechniques, areutilizedenabling CSoptimizationstobeperformedinalargerscope thaninpreviousapproaches.Extensiveexperimentalevaluationsshow thattheproposedacceleratorarchitecturedeliversaveragegainsofup to 61.91%in area-delay productand54.43%in energy consumption comparedwiththestate-of-artflexibledatapaths. In this paper, their concentration is on 16 bit operations but here in the proposed scheme, the focus is on 32 bit operations.Hardware Acceleration basically refers to the usage of computer hardware to perform some functions faster than they are actually possible within the software running on general purpose CPU. TheRISCor ReducedInstructionSetComputerisadesignphilosophythathasbecomeamainstreaminScientificandengineeringapplications.Themainobjectiveofthispaperis to design and implement of 32 – bit RISC(ReducedInstruction Set Computer) processor forflexible DSP Accelerator Architecture.Thedesignwillhelp to improve the speed of the processor, and to give thehigherperformance of the processor. The most important featureofthe RISC processor is that this processor is very simpleandsupport load/store architecture. The important componentsofthis processor include the Arithmetic Logic Unit,Shifter,Rotator and Control unit. The module functionalityandperformance issues like area, power dissipationandpropagation delay are analyzed. Therefore, here we meet some of the main constraints likeComplexity of the instruction set, which will reduce the amount of space, time, cost, power, heat and other things that it takes to implement the instruction set part of a processor. As the Time of execution decreases, the Speed of execution automatically increases.Hardware acceleration has been proved an extremely promisingimplementation strategyforthedigitalsignal processing(DSP) domain.Ratherthanadoptingamonolithicapplication-specificintegrated circuit designapproach,  in thisbrief, we present a  novel accelerator architecture comprising flexiblecomputational  units that support the executionofalargesetofoperationtemplatesfoundinDSPkernels. Wedifferentiatefrompreviousworksonflexibleacceleratorsbyenabling computations tobeaggressivelyperformedwithcarry-save(CS)formatteddata.Advancedarithmeticdesignconcepts, i.e.,recodingtechniques, areutilizedenabling CSoptimizationstobeperformedinalargerscope thaninpreviousapproaches.Extensiveexperimentalevaluationsshow thattheproposedacceleratorarchitecturedeliversaveragegainsofup to 61.91%in area-delay productand54.43%in energy consumption comparedwiththestate-of-artflexibledatapaths. In this paper, their concentration is on 16 bit operations but here in the proposed scheme, the focus is on 32 bit operations.Hardware Acceleration basically refers to the usage of computer hardware to perform some functions faster than they are actually possible within the software running on general purpose CPU. TheRISCor ReducedInstructionSetComputerisadesignphilosophythathasbecomeamainstreaminScientificandengineeringapplications.Themainobjectiveofthispaperis to design and implement of 32 – bit RISC(ReducedInstruction Set Computer) processor forflexible DSP Accelerator Architecture.Thedesignwillhelp to improve the speed of the processor, and to give thehigherperformance of the processor. The most important featureofthe RISC processor is that this processor is very simpleandsupport load/store architecture. The important componentsofthis processor include the Arithmetic Logic Unit,Shifter,Rotator and Control unit. The module functionalityandperformance issues like area, power dissipationandpropagation delay are analyzed. Therefore, here we meet some of the main constraints likeComplexity of the instruction set, which will reduce the amount of space, time, cost, power, heat and other things that it takes to implement the instruction set part of a processor. As the Time of execution decreases, the Speed of execution automatically increases