0.18 mu m CMOS power amplifier for Ultra-wideband (UWB) system

Abstract

This paper presents the design and implementation of a single-stage and double-stage power amplifier (PA) for UWB communication system. The proposed PAs are implemented in 0.18 mu m CMOS integrated circuit technology for a 3.1-4.8GRz UWB system. The single-stage PA achieves a simulated maximum power gain of +10.4dB at an input P1dB of -5.5dBm while consuming 23.0mW of DC dissipation at a DC supply of 1.0V. Two double-stage PAs have been designed based on the single-stage PA topology. Simulation results for both the double-stage PAs show a maximum power gain of +15.5dB and +24.1dB respectively with the power consumption of 35.5mW and 26.7mW separately. Results obtained from this study can be used as a reference design for future multi-stage UWB PAs implementation