This paper presents the physics-based variability analysis of multi-fin double-gate (DG) MOSFETs, representing the core structure of FinFETs for RF applications. The variability of the AC parameters as a function of relevant geometrical and physical parameters, such as the fin width, the fin separation, the source (drain)-gate distance and the doping level is investigated. The analysis exploits a numerically efficient Green’s Function technique [1]-[2], extending to the RF case the linearized approach well known from DC variability analysis. The variability of a single fin DG-MOS transistor is compared to a more realistic structure with two fins and raised source/drain contacts, i.e. including both the active part of the FinFET and a significant amount of passive (parasitic) components at the device level. Although presently implemented in a 2D in-house software, the technique can be easily exported to standard 3D TCAD tools, e.g. for tri-gate FinFETs analysis

Bonani, F.

Bughio, A. M.

Donati Guerrieri, S.

Ghione, G.

English

BUGHIO, AHSIN MURTAZA

DONATI GUERRIERI, Simona

BONANI, FABRIZIO

GHIONE, GIOVANNI

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

04 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEPhysics-based modeling of FinFET RF variability / Bughio, A. M.; Donati Guerrieri, S.; Bonani, F.; Ghione, G.. - (2016).((Intervento presentato al convegno European Microwave Integrated Circuits Conference (EUMIC) tenutosi a London,UK nel 3-7 October 2016.OriginalPhysics-based modeling of FinFET RF variabilityPublisher:PublishedDOI:Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2653327 since: 2016-10-18T10:33:19ZIEEEPhysics-based modeling of FinFETRF variabilityA. M. Bughio1, S. Donati Guerrieri1, F. Bonani1, G. Ghione11Dipartimento di Elettronica e Telecomunicazioni, Politecnico di TorinoCorso Duca degli Abruzzi, 24, I-10129 Torino, ITALYAbstract—This paper presents the physics-based vari-ability analysis of multi-fin double-gate (DG) MOSFETs,representing the core structure of FinFETs for RFapplications. The variability of the AC parameters as afunction of relevant geometrical and physical parameters,such as the fin width, the fin separation, the source(drain)-gate distance and the doping level is investigated.The analysis exploits a numerically efficient Green’sFunction technique [1]-[2], extending to the RF casethe linearized approach well known from DC variabilityanalysis. The variability of a single fin DG-MOS tran-sistor is compared to a more realistic structure withtwo fins and raised source/drain contacts, i.e. includingboth the active part of the FinFET and a significantamount of passive (parasitic) components at the devicelevel. Although presently implemented in a 2D in-housesoftware, the technique can be easily exported to standard3D TCAD tools, e.g. for tri-gate FinFETs analysis.Index Terms—FinFET, Variability, Numerical simula-tionsI. INTRODUCTIONFinFETs have become the leading devices forCMOS applications, allowing for a higher immunityto short channel effects with respect to their com-petitors (UTB-SOI). A significant key to the successof FinFETs relies in their 3D structure allowing forcompletely new scaling features and device architec-ture. Despite the enormous amount of work dedicatedto the fabrication, optimization and modeling of thesedevices, comparably less effort has been dedicated totheir AC characterization and modeling [3], althoughthe interest towards analog RF and microwave appli-cations fosters research in this field. The peculiar 3Dstructure of the device can obscure the RF advan-tages brought by the gate length reduction becauseof a considerable amount of parasitic capacitancesand resistances [3] that have a milder effect, or aretotally absent, in the standard MOS technologies. Sincevariability is known to significantly impact the DCdevice behavior, the same is expected for the ACperformance, both at the active device and at theparasitics level. Furthermore the multi-fin structureused for RF FinFETs makes the separation of thedevice active and passive parts difficult already for theintrinsic device. In fact, some geometrical variationsmay have a small impact on the DC characteristics butaffect the AC variability, e.g. through capacitances. Itis therefore mandatory to devise reliable and efficienttools allowing for the evaluation of AC performancevariations as a function of the most important physicalparameters of the FinFET structure.For accurate variability estimation, physics-basedanalysis through TCAD tools is the most importantway to link a device performance variation to a phys-ical or geometrical parameter variation ([1], [2] andreferences therein). Unfortunately, variability analysisthrough the so-called incremental approach, i.e. re-peating the device analysis by changing the parameterwithin a prescribed range, usually corresponds to ahighly intensive numerical effort and is especiallydifficult for devices with complicated geometries, likemultiple fin devices, or with randomly distributedparameter fluctuations. A breakthrough has been thedevelopment of Green’s Function (GF) based tech-niques, which rely on linearized model analysis and arehence extremely numerically efficient. Besides beingapproximated, the GF approach has been proven tobe accurate for the DC device variability even forextremely scaled devices [1], [4]. Currently the GFapproach is limited to the DC variational analysis,like the one implemented in Synopsys [4]. Recentlya methodology extending the GF approach to the ACcase has been presented [2], to evaluate the sensitivityof the AC admittance matrix with negligible numericaleffort with respect to the ordinary device simulationtime. While in [2] only test case structures are reported,in this paper we present preliminary results concern-ing the RF variability analysis of more realistic DGdevices, as the preliminary step towards the completeFinFET variability analysis. A single fin device and adouble fin one, including the finger cross-couplings andpart of the raised source/drain and gate couplings, arecompared. The variation of the AC admittance matrixelements is presented as a function of the fin width,drain extension length, source/drain doping and finseparation. Comparison with the incremental analysisshows that the proposed approach is valid up to 20%of variation of the parameters, hence validating theproposed approach.II. GREEN’S FUNCTION APPROACH TO ACSENSITIVITY ANALYSISIn this paper we exploit the physics-based ACsensitivity analysis introduced in [1]-[2]. The startingpoint is the Large Signal (LS) physics-based modelin [5], allowing for Harmonic Balance based multiff0F{s(t)}ff0F{i(t)}2f0 3f0 4f0AC sensitivityDC sensitivityFig. 1. Schematic representation of the variability modeling ap-proach. s(t) is a terminal applied voltage, i(t) the terminal current,F the Fourier transform.tone device simulation including efficient GF analysiscapability. The physical model is solved with a smallamplitude AC tone Vj,AC at frequency f0 and eachterminal j superimposed to DC bias. In principle allthe harmonics nf0 should be included in the simulationspectrum but the AC tone is so small that the analysiscan be limited to n = 0, 1 (see Fig. 1): hence the extranumerical effort for the system solution is negligiblewith respect to the simple DC analysis. The solutionreturns the AC device currents Ik,AC at each terminal k,see Fig. 1, allowing for the direct evaluation of the ACadmittance without any need of model linearization:Yk,j =Ik,ACVj,AC.The system is then linearized to account for the change∆σ of any given parameter σ: keeping the voltagesources at the terminals unchanged, the short circuitvariation of the current phasor ∆Ik,AC, induced by ∆σ,is recovered by the GF technique. Finally, the variationof the admittance matrix elements ∆Yk,j is simply:∆Yk,j =∆Ik,ACVj,AC. (1)Notice that the system, both the one with the nominalparameter σ and the one with variations, is solvedwith simultaneous DC and AC excitations (see Fig. 1):therefore, even though in this paper we will focus onthe AC device response, it is worth noticing that theproposed GF approach allows for the simultaneous DCand AC variability analyses.III. CASE STUDY 1: SINGLE FIN DG DEVICEThe above analysis has been applied to a single finDG structure, shown in Fig. 2, left, representing a 2Dcross section of a tri-gate FinFET. The quantities to bevaried are: the fin width (WF), the gate/source(drain)distance (LDE) and the source/drain (S/D) doping(DOP), see Fig. 2 for the exact definition and geometry.These parameters have been selected since they impactin particular the parasitic resistance of the fin, thusplaying an important role in determining the RF deviceperformances. With the aim of a possible developmentof a small-signal high gain or of a low noise amplifierfor small-cell applications, the operating frequencyhas been fixed to 60 GHz and the bias condition isVGS = 0.6 V and VDS = 1 V corresponding to a draincurrent of 0.4 mA/mm.In Fig. 3 the real part of the drain-gate element ofthe admittance matrix is plotted against the percentagesingle fin device(cross section in the plane)x-ydouble fin device(cross section in the plane)x-yLPLPWSWFLDEWFWSWS/2LDEinnergateexternalgateexternalgateSourceDrainLPN =5 x10D18N =5 x10D18N =10A15LDELPWS/2WFLDEN =5 x10D18N =5 x10D18N =10A15LDELGTOXDDG1G2N =10D20equivalent SiO TOX2 1 nmLDE 54 nmLG 54 nmWF 10 nmWS 36 nmLP 54 nmLGXYZN =10D20Fig. 2. Single fin DG MOSFET (left) and double fin DG structure(right). Green areas represent Si regions, the light blue SiO2 andyellow the metal gates.% variation-20 -10 0 10 2033.23.43.63.8TotalDGadmittance,S/mmWFLDEDOPFig. 3. Real part of the drain-gate admittance for the single fin DGdevice vs. parameter variations.parameter variations (this element is of course relatedto the total transconductance). It is evident that nearlyexact tracking of the variations is observed for bothDOP and WF: the variation is significant and around10%, thus suggesting that the parasitic resistance ofthe S/D region heavily affects the transconductance.Increasing DOP and WF reduces the parasitic resis-tance: the admittance variation is approximately lin-early increasing with these quantities and with nearlythe same slope. Of course, the opposite is observedwith increasing the S/D-gate separation LDE. Noticethat in this figure, and in the following Figs. 5-8,the contributions of the two gates are summed toemulate the FinFET behavior, where the two contactsare effectively shorted. For validation, the results fromthe GF approach are always reported compared tothe much more computationally intensive incrementalanalysis (symbols in the figures). The accuracy of theGF approach is verified even for parameter variationsup to 20% with respect to the nominal values.% variation-20 -10 0 10 20681012TotalDDadmittance,mS/mmWFLDEDOPFig. 4. Real part of the drain-drain admittance for the single fin DGdevice vs. parameter variations.Fig. 4 shows the variation of the real part of thedrain-drain element of the admittance matrix. Hereas well the variation is quite significant. While thegeneral trend is maintained with respect to the DGelement, the effect of DOP is highly reduced whilethe WF effect is dominant. In fact, the dependencyof the output conductance on DOP and LDE is justthrough the parasitic resistances and short channeleffects. Remarkably, the DOP dependence is milder.A possible interpretation is that DOP reduces theparasitic resistance but increases the short channeleffects: the two effects have opposite influence on theoutput conductance. Notice that this parameter, despitebeing quite negligible for digital applications, plays asignificant role for analog applications.Turning to the imaginary parts, Fig. 5 shows thecapacitances of the gate-gate (top), gate-drain (middle)and drain-drain (bottom) elements, i.e. the imaginarypart divided by the angular frequency. Notice that thepercentage variation with respect to the nominal valueis lower, limited to a few percent in the case of thegate-gate and gate-drain elements: this is due to thefact that the considered variations impact mainly onthe parasitic capacitances which are in any case a smallamount with respect to the total capacitance, dominatedby the gate oxide. For the total GG capacitance WF andDOP variations are again closely correlated, suggestingthat the parasitic source resistance dominates over theintrinsic access resistance, while the DG capacitanceis less affected. The output capacitance, see Fig. 5,bottom, despite smaller, is known to be mostly ageometrical capacitance and has the most significantdependence on the parameter variation.Finally, Fig. 6 shows the cut-off frequency behavior:fT traces the transconductance variations, but the effectof the gate-gate capacitance makes the fT spreadlimited to around 6 GHz in this case. Notice thatthe single fin device is stripped by most capacitiveparasitics, that will be shown in the following, hencethe cut-off frequency value is extremely high.% variation-20 -10 0 10 201.61.651.71.751.8TotalGGcapacitance,pF/mm WFLDEDOP-20 -10 0 10 200.920.940.960.981TotalDGcapacitance,pF/mm% variationWFLDEDOP-20 -10 0 10 20404550556065TotalDDcapacitance,fF/mm% variationWFLDEDOPFig. 5. Total gate-gate (top), drain-gate (middle) and drain-drain(bottom) capacitance of the single fin DG device vs. parametervariations.IV. CASE STUDY 2: DOUBLE FIN DG DEVICETo better highlight the capability of the proposedapproach we consider here a two fin device, withthe source and drain contacts joined to emulate theraised S/D contact of a realistic FinFET device, seeFig. 2, right. Here the geometry of the two intrinsicfins is the same as in the previous case. The DC draincurrent exhibits good scaling with respect to the singlefin case, however this structure allows for the inves-tigation of extra parasitics. In the multi-fin case theparasitic network identification through measurementdeembeding or conformal mapping is a difficult and-10 -5 0 5 10322324326328330332f T,GHz% variationWFLDEDOPFig. 6. Cut-off frequency of the single fin DG device vs. parametervariations.cumbersome task [3], [8], while TCAD tools are theideal environment to simultaneously include all the pe-culiarities of these devices. In fact, the reduced size ofthe FinFETs allows for the concomitant simulation ofthe multiple fins together with the inner portion of theirinterconnects, as demonstrated e.g in the simulation ofwhole SRAM cells in DC [6], [7].Turning to the variability analysis of the device inFig. 2, besides the variations of WF, LDE and DOPlike in the previous case, we address also the finseparation WS. Globally the capacitances of the doublefin device are found to be higher than the ones of thestripped single fin case due to the sidewall source anddrain regions. Comparing the total gate-gate and gate-drain capacitances of the two-fin DG MOS with theprevious stripped device (scaled by an ideal factor oftwo), a rough estimate of 0.5 pF/mm for each sideof the gate (source/drain) can been made: this amountadds to the drain-gate capacitance and double of it(source+drain) to the total gate-gate capacitance. Whilethis is just a crude estimation found by comparison ofthe two devices, the capacitance found from TCADis instead accurate. It includes all fringing effectsand their (possibly complicated) dependency on thegeometry. The same is true for the variation analysis.Here only selected results are shown for brevity. Fig. 7,for example, shows the drain-gate behavior: unlike thecase of the stripped device, here the fin width separa-tion WS and LDE play a major role with respect toDOP and WF, hence highlighting the strong influenceof the parasitic capacitance. Finally Fig. 8 shows thecut-off frequency as a function of all parameters. Herethe effect of WS is found to be close to that of WF andDOP, showing the complicated interconnection of thetransconductance variations combined with the totalgate capacitance, which increases with WF, WS andDOP and decreases with LDE (not shown for brevity).V. CONCLUSIONSWe have demonstrated an efficient TCAD tool forthe FinFETs AC variability analysis. The variability-10 -5 0 5 10% variation2.422.432.442.452.462.472.48TotalDGcapacitance,pF/mmWFLDEDOPWSFig. 7. Drain-gate capacitance of the two-fin DG structure.-10 -5 0 5 10% variation258260262264266268270f T,GHzWFLDEDOPWSFig. 8. Cut-off frequency of the two-fin DG device.of a single and double fin DG MOSFETs have beenpresented with focus on the parasitics affecting theRF behavior. The source/drain parasitic resistance vari-ability has a significant impact both on the single fintransconductance and output conductance, and on thegate capacitance. The double fin structure is heavilyaffected by the extra gate-source (drain) capacitancesand the fin width separation becomes the dominantvariability source, especially compared to the gate-source (drain) separation. Other possible geometrieswill be considered in the full paper.REFERENCES[1] S. Donati Guerrieri, et. al., IEEE Trans. El. Dev., Vol. ED-63,No. 3, pp. 1195–1201, March 2016.[2] S. Donati Guerrieri, et. al. IEEE Trans. El. Dev., Vol. ED-63,No. 3, pp. 1202–1208, March 2016.[3] G. Crupi, et. al., Solid-State Electronics Vol. 80, pp. 8195,February 2013.[4] Synopsys, Inc. Sentaurus Device. [Online]. Available:http://www.syn opsys.com/Tools/TCAD/DeviceSimulation/-Pages/SentaurusDevice.aspx[5] F. Bonani, et al. , IEEE Trans. El. Dev., Vol. ED-48, No. 5, pp.966–977, May 2001.[6] K. El Sayed et. al., Vol. ED-59, No. 6, pp. 1738–1744, June2012.[7] N. Agrawal, et. al., IEEE Trans. El. Dev., Vol. ED-62, No. 6,pp. 1691–1697, June 2015.[8] K. Lee, et. al. IEEE Trans. El. Dev., Vol. ED-60, No. 5, pp.1786–1789, May 2013.

Physics-based modeling of FinFET RF variability

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Physics-based modeling of FinFET RF variability

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