In this paper are described some of the issues of the mixed signal standard cell VLSI design with emphasis on the practical experience resulted from designing a carrier transceiver in SGS-THOMSON 2 μm BiCMOS technology. Presented are the circuit block structure, some advantages and disadvantages of the standard cell design approach, the testing strategy we implemented, and finally some practical conclusions resulting from our experience

Civera P.

Lazarescu M.T.

Sartori M.

English

LAZARESCU, MIHAI TEODOR

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

04 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEDesign issues of a standard cell BiCMOS carrier transceiver on low voltage power lines / Lazarescu M.T.;SartoriM.;Civera P.. - ELETTRONICO. - (1995), pp. 375-380. ((Intervento presentato al convegno Semiconductor Conference1995 (CAS '95) tenutosi a Sinaia, Romania nel October 1995.OriginalDesign issues of a standard cell BiCMOS carrier transceiver on low voltage power linesPublisher:PublishedDOI:10.1109/SMICND.1995.495040Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2507493 since:IEEE / Institute of Electrical and Electronics Engineers Incorporated:445 Hoes Lane:Piscataway, NJ 08854:Design Issues of a Standard CellBiCMOS Carrier Transceiveron Low Voltage Power Linesing. Mihai T. LAZARESCUPolitecnico di Torinoc.so Duca degli Abruzzi, 2410129 TURIN, ITALYemail: lazarescu@polito.iting. Mario SARTORIPolitecnico di Torino, COREP { LETEOprof.dr. Pier Luigi CIVERAPolitecnico di Torino, ITALYABSTRACTIn this paper are described some of the issues of the mixed signal standard cellVLSI design with emphasis on the practical experience resulted from designing acarrier transceiver in SGS-THOMSON 2m BiCMOS technology. Are presented thecircuit block structure, some advantages and disadvantages of the standard celldesign approach, the testing strategy we implemented, and nally some practicalconclusions as resulted from our experience.1 IntroductionIn the middle of the informational explosion of our days, the communications are essential. Weassist at a boom of the communication equipment oer, the products on the market featuringa huge diversity in performances. In this conditions the product time-to-market is of crucialimportance and the design approach should be chosen taking this aspect into account. More-over, for ASIC circuits it is very important to reduce the NRE (Non Recurrent Expenses), thatis to have a bug-free and specications compliant design at the rst or after very few runs.To achieve this goal the design process should be as much as possible supervised by automaticCAD tools such as simulators, electric and layout rules checkers, synthesis tools for the digitalparts and for switched capacitor circuits, etc.For mixed ASIC design, the standard cell (SC) approach is the most complying to thisrequirements. The foundries oer of mixed mode signal SC is widening and diversifying givinga better choice of performance in order to match tighter design requirements. Fast analogmodels are also provided that, together with ecient mixed mode simulators and powerfulFigure 1: Carrier transceiver block schematiccomputers make possible the simulation of large parts of the circuit as a whole allowing abetter check of the functionality and specications compliance of the design.The SC libraries hidden the most of the boring and very time consuming layout relatedissues to the designer allowing a larger part of the design time to be allocated to system andfunctional issues. This way the design time and NRE are considerably reduced with betterspecication compliance.In this paper will be presented the main characteristics of a mixed signal design. Theparticularities of the SC approach will be emphasized. The practical experience of a carriertransceiver design using the standard cell approach in the 2m BiCMOS technology of SGS-THOMSON will be used to annotate the presentation.2 System block schematicThe block schematic of the carrier transceiver as represented in the ADS design environmentof SGS-THOMSON is reported in gure 1. It is composed of the following main subsystems:Frequency synthesis block which generates all the square wave frequencies used by otherblocks in the circuit both in RX and in TX operation modes. This block in turn iscomposed of: a crystal chain which generates several xed frequencies; two programmable PLL frequency synthesisers, one of which with testing facilitiesembedded; preset registers storing values of the constants corresponding to the various frequen-cies PLLs have to generate.Common TX/RX blocks part that contains most of the transmission blocks which can be reusedin RX mode. It is composed of: a sine wave synthesizer composed of a 16-states Finite State Machine (FSM) drivinga dedicated D/A converter; a logic block synchronized with sine wave zero crossing with positive derivate toswitch the input of the FSM from one PLL to the other according to the value of theinput data; a radio frequency switched capacitor lter with antialiasing and smoothing continu-ous time lters; bidirectional test points placed before and after the sine wave generator.TX that contains only the transmission output buer, which is the only TX dedicated block;RX that contains almost all the receiver chain (excepting the input switched capacitor ltershared with the transmission part): an analog multiplier acting as frequency mixer to scale down the received signalfrequency; an Intermediate Frequency (IF) switched capacitor lter with smoothing and an-tialiasing continuous time lters; two signal ampliers rising the receiver gain to 21dB; several high-pass lters to reject the DC oset along the chain; an externally programmable hysteresis comparator; a digital demodulator and carrier detect circuit; test points after the analog multiplier and before entering the hysteresis comparator.TX/RX logic containing operation mode switching logic, power-on reset, transmission time-out, etc.The block functional description above was given to make an idea of the complexity andthe dimensions of the project. Despite that, due to standard cell approach of the design, theuse of a high level synthesiser and silicon compiler for the switched capacitor lters design, andof the logic, electric, and mixed mode simulation facilities available under the SGS-THOMSONADS design environment, the chip design was completed in one year time with the continuouswork of approximately one full-time person. The chip size is 28mm2.3 Mixed signal standard cell approach main issuesThere is a great deal of particularities of the standard cell design of mixed mode circuits. Nextwe will try to summarize some of the most important we have met during this project.First of all it is to be noted that the library cells available are pushing the designer towardsa design style and solutions that are very close to the usual discrete components ones. Themain advantages of this design style are: the use of the high level cells available in the library leads to a safer design. Unlike thedesign at transistor level when the designer has the whole responsibility for the designrelying only on the previous experience and on the simulations result, each of the librarycells is well tested and characterized by the foundry that guaranties its performances andthe accuracy of the simulations results based on extensive test runs; for the analog standard cells fast simulation macromodels are provided that can be usedto run electrical simulations on large subsystems in order to check the proper operationof the individual blocks once interconnected. If on the contrary, the design is made attransistor level, only small size circuits can be simulated and load eects or large loopswith long transients (such as a PLL) pose serious simulation constraints; when operating with high level functional blocks to design the circuit, the designer doesnot have to cope anymore with circuit and layout details such as transistor sizes andmatching, etc., but can pay more attention instead to system issues, block implementa-tion, design for testability, etc.; the ease of building blocks with standard cells oers the designer the possibility to realize,simulate, and compare dierent implementations of the same circuit block and to choosethe most suited structure for each particular case. Circuit modications can be madeeasily and safely in case of changes in specications or added features; the enormous amount of time saved designing with standard cells can be used to ex-tensively simulate large parts of the circuit in full temperature range and technologicalprocess spread, increasing this way the probability of a rst time working and reliablecircuit.The most important drawback of the standard cell design approach is that it is not possibleto exploit the whole resources of a given technology. This is why blocks may need a transistorlevel design using either single transistors (with a few choice of dimensions), current mirrors,etc. provided as standard cells in the library or taking the whole freedom in dening a fullcustom layout for some blocks. It is better to avoid the last solution, but the choice depends onhow many \elementary" cells (like single parametrized transistors, current mirrors, dierentialstages, etc.) are available on the library.All the standard cells of the same type have the same height. Usually the analog cells arehigher than the digital cells what causes analog and digital cells to be placed in dierent rows inthe layout. Since there is always some small amount of logic to be placed near the analog cells(such as inverters used as output buers for analog comparators, buers for the power downsignal for the analog cells, etc.), the ADS environment library oers digital cells with analogheight, that can be abutted in analog rows. The designer has to take care to place this specialtype of cells whenever required and to specify the same supply as for the analog cells they haveto stay with on the layout to avoid a long routing from the digital part of the layout.The switched capacitor lter synthesiser and compiler proved to be of great help in thedesign. Using these tools it is possible starting from a high level description of the lter mask,zeros and poles position, etc. or any valid SWITCAP1netlist to semi-automatically generate thewhole layout of the switched capacitor circuit providing the designer with a SWITCAP netlist(if synthesis was started from a high level lter description) and with the schematic capture ofthe circuit ready to be simulated with an electrical simulator.1SWITCAP is a simulator dedicated to switched capacitor circuits simulation developed at Columbia Uni-versity, New York, U.S.A.4 TestingEven designing with standard cells we cannot be sure to avoid all the design errors therefore weplaced in the circuit several test points creating an ecient test structure. The observabilityand testing features are very important for a new design because they ease the chip debuggingand redesign.Besides the normal inputs and outputs of the circuit we placed several analog and digitalIO test pads activated with special external test signals in the key points of the circuit aftera long observability analysis. The test point capabilities are to monitor the signal that passesacross them or to cut it and supply a signal from outside as input for the following block.The test point disposition in the circuit was carefully chosen also with the target of allowingfor the important subsystems the injection of an externally synthesized signal that emulate theoutput of the preceding block so that the rest of the circuit can be tested in normal operationeven if one or several block failure occurs.A rst analog IO test point is placed in the loop of one of the PLLs (see gure 1). It allowsmonitoring the command voltage of the VCO and to impose externally the command voltagein order to extract the VCO voltage-frequency characteristic or in case of PLL failure.A digital IO test point is placed before the sine wave shaper. This point can monitor theoutput frequencies of the two PLLs and can also force an external input frequency for the sinewave shaper in case of general failure of both PLLs. If one of the external A or B signals arebecoming active, this test point can be used also to provide from outside the sampling frequencyfor the switched capacitor lters.The output of the sine wave shaper is monitored by an analog IO test point so that inconjunction with the preceding test point the sine wave shaper can be isolated and testedindependently from the rest of the circuit. This test point is used in transmission mode to forcethe input of the common TX/RX switched capacitor lter while monitoring the output of thesame lter at the TX output pad. In RX mode it can be used to feed the locally generatedfrequency into the multiplier while the other mixer input is injected from the normal RX inputpad.Another analog IO test point is placed at the output of the analog multiplier. This can beused to monitor the output of the multiplier for test purpose and also to inject an externalsignal into the input of the IF chain.At the end of the IF chain is placed the last test point, an analog IO. This is designed tocheck the whole IF chain in pair with the test point at the output of the multiplier. It can alsosupply an external signal to the hysteresis comparator to check its functionality, the hysteresisvalue, and the hysteresis external regulation. Moreover, it is used to provide test signal forthe digital demodulator and carrier detect circuits via the hysteresis comparator. The normaloperation of the digital blocks can be inspected at the outputs of the receiver and of the carrierdetect circuit.5 ConclusionsThe practical experience of designing a complex mixed signal circuit using a standard cellapproach showed us that the SC design style is very ecient. Of course, this eciency is paidin larger designs and in constraints regarding the choice of the circuit solution.We encountered however dierent kinds of problems during the design and some of themcould be avoided by a careful initial check of the design environment and through a selection ofthe foundry with respect not only to technology performance but also to completeness of thelibraries and cells electrical specications: we need for the PLL VCO high performances so we had to design part of them at transistorlevel, that is using standard cell transistors and current mirrors. This increased the riskof non functioning for this block because of process and temperature spread so we had toprovide external adjustments to compensate this inuences; the ADS environment did not provide a logic circuit synthesiser so we had to design all thelogic parts by hand. As the digital part of this circuit is quite complicated, this processtook us a lot of time and can become easily a source of errors; the switched capacitor silicon compiler did not check all the user input creating thepossibility of human-introduced errors; fast simulation models for some analog cells proved to be erroneous or to have a badconvergence in mixed mode simulations; the ADS library documentation was faulty or confuse sometimes; some of the simulators provided with the design environment had bugs and could not beupgraded because of version incompatibility.Despite these drawbacks we do believe we have chosen the best technology{design environ-ment trade-o taking into account the complexity and the narrow specications of the chip.References[1] Yannis Tsividis, Paolo Antognetti, Design of MOS VLSI Circuits for Telecommunications,Prentice-Hall, Inc., 1985, pp. 512-544[2] John A.C. Bingham, The Theory and Practice of Modem Design, John Willey & Sons,Inc., 1988[3] Roland E. Best, Phase-Locked Loops, McGraw-Hill, Inc., 1993[4] S.J. Daubert & al., A CMOS Modem Analog Processor for V.22bis Modems, IEEE Journalof Solid States Circuits, April 1989, vol. 24, no. 2[5] S.D. Levy & al., A Single-Chip 5-V 2400-b/s Modem, IEEE Journal of Solid States Circuits,June 1990, vol. 25, no. 3[6] J.J.J. Haspeslagh & W.M.C. Sansen, A Total Solution for a 9600-b/s Modem TransmitterChip, IEEE Journal of Solid States Circuits, June 1990, vol. 25, no. 3

Design issues of a standard cell BiCMOS carrier transceiver on low voltage power lines

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Design issues of a standard cell BiCMOS carrier transceiver on low voltage power lines

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