Althaus, R.F.

Kirsten, F.A.

Lee, K.L.

Wagner, L.J.

eScholarship - University of California

Lawrence Berkeley National LaboratoryRecent WorkTitleON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATIONPermalinkhttps://escholarship.org/uc/item/7fw5g8mcAuthorsAlthaus, R.F.Lee, K.L.Kirsten, F.A.et al.Publication Date1973-05-01eScholarship.org Powered by the California Digital LibraryUniversity of CaliforniaPresented at International Conference on Instrumentation for High Energy Physics, Frascati, Italy, May 8-12, 1973 ON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATION R. F. Althaus, K. L. Lee, F. A. Kirsten, and L. J. Wagner May 1973 Prepared for the U.S. Atomic Energy Commission under Contract W -7405-ENG-48 For Reference Not to be taken from this room LBL-1750 c.\ DISCLAIMER This document was prepared as an account of work sponsored by the United States Government. While this document is believed to contain correct information, neither the United States Government nor any agency thereof, nor the Regents of the University of California, nor any of their employees, makes any warranty, express or implied, or assumes any legal responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by its trade name, trademark, manufacturer, or otherwise, does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof, or the Regents of the University of California. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof or the Regents of the University of California. f .. ·' ·.y J ON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATION* R. F. Althaus, K. L. Lee, F. A. Kirsten and L. J. Wagner Lawrence Berkeley Laboratory Univers ity of California Berkeley, CA 94720 l. -Summary Commercially available high speed digital integrated circuits (I.C . 's) now have performance characteristics and economy that make them . attractive as central l ogical elements around wh1~h state-of-the-art instruments for High_Energy Phys1~') can be developed. In work reported f1ve years ago commercial I .C. • s were shown to offer advantages ?f economy and packaging density, which were valued 1n some 1 arge system arrays, but thci r performance v1as below that of the 200 MHz commercially available counting equipment. No longer must speed, or re-. solution, be compromised for these advan~~ges. Clr-cuits now configured around the Motorola MECL III line of integrated circuits pr?vide 3~0 ~Hz speed, 1.2 ns maximum rise- or fall-t1me, colnclde~ce_re­cognition for 1 ns overlap, and inherent ~o1nc1dence time resolution edges of less than 40 ps (1000:1 count rate). Two modular packaging schemes using !~ECL III I.C. 's have been developed at the Lawrence Berkeley Laboratory. The first to be descri~ed, cal ~ed the FLOGIC System, achieves high packag1ng dens1t~ by means of logic cards that are interconnected 1n a custom design unique to each experiment. The FLOGIC System is most suitably used where many c~annel~ of instrumentation are required and the conf1gurat1on of these channels, once established, is not subject to frequent unprescribed change. The second scheme uses th.e NIM Standard(2) hardware. This scheme offers the convenience and versatility of standardized hardware and signal levels. 2. - THE FLOGIC System The FLDGIC System is modular at the printed circuit card level. Small (55mm X ll4mm) printed circuit cards containing I.C. gates and registers are interconnected to perform the logical functions desired for a specific application. Achieving this modularity in a manner consistent with t~e perform~nce characteristics of the MECL I.C. 'sand w1th economl-cally practical hardware were the dichotomo~s ob-jectives of this system. Sub~iniat~re coax~al connec-tors as a natural first cons1derat1on for lnter-conn~ction, match the performance characteristi~s, . but are prohibitively expensive and leave the dlstrl-bution of d.c. power as a separate consideration. *Work done under the auspices of USA EC **Motorola Semiconductor Products, Inc. Phoenix, Arizona, U.S.A. -1-Unique utilization of standard commercial com-ponent parts pro vi des performance at an attractive cost. Interconnection is accomplished by means of DIAD connectors, an adaptation of the Termi-twist/ Termi-point printed circuit card-edge connector series manufactured by AMP.* The overall system is packaged in bins available from Data-Tech.** Power can be provided by any modular floating 5.2V power supply; a floating supply is used to shift the usual MECL III logic signal levels of -0.8V and -l.6V to approximately OV and -0. 8V, compatible with the NH·l standard. 2.1 - MECL III FLOGIC cards Figure l shows a MECL III FLOGIC card in which you can see the strip-line input and output fast sig-nal lines required by the nominally l ns signal tran-sition speed of the I.C. 's. Output signal strip-lines have a characteristic impedance (Z0 ) of 50n; they are the four wide strip-lines on the card. Pulldown resis-tors of l80n for each of these outputs are located adja-cent to the I.C. Inputs, the eight narrow strip-lines, are run at lOOn Zo to conserve on printed surface area; these lines are shunted with lOOn resistors at the card-edge to terminate the 50n input coax, and are terminated at the I.C. with a l OOn strip-line match. As a shadow, you can see the plane cond~ctor surface on the reverse side of the card that serves as refer-ence for the strip- li nes. The lower portion of this plane surface is at common potential, but the upper portion is at -4.4V, Vee. as required for the stud connection on the I.C. A row of capacitors provides a . c. signa l continuity across these two plane sur-faces. The remaining trace is the +0.8V, Vee conductor. 2.2 - DIAD Connectors Figure l also shows the interconnecting hardware. Inexpensive Termi-point clips are solder-mounted onto the sma ll printed pads shown at the top of the figure to produce DIAD connectors as shown in front and rear views in Fig. 2. The pads have a ~lane surface on one side, to which the coax braid is referenced. On the other side, to v;hich the Termi-point clips are soldered, a strip-line is printed as the signal con-ductor. A capacitive mismatch at th e clip end of the DIAD, caused by the very presence of the clips, is used to advantage. It is trimmed, by voiding a section of the rear plane surface, to just combine with a small inductive lump in the rearward pin extension of the Termi-twi st connector socket contact and a capacitive lump at the forward ex tension of the contact (due to dielectic effects of the connector block) to provide a C-L-C lumped constant section of 50n line with transit *AMP Incorporated, Harrisburg, Pennsylvania, U.S.A. **Data Technology, Corp., Palo Alto, California, U.S.A. -2-li Fig. 1. MECL III Fl og i c Sys t em Components Fig. 2. DIAD Connector for MECL III FLOGIC System time short enough to be inconsequential to the 1.2 ns rise-time signal out of the MECL III I.C. 's, when driving a 50n load. Tests show this compen-sated DIAD connector to pass a 200 ns 10-90% rise-time signal with undetectable deterioration of 10-90% rise-time, whereas an uncompensated version, with the same Termi-point clip, deteriorat~s the 200 ps 10-90% rise-time to 700 ps. 2.3 - A FLOGIC Instrumented Experiment An experiment implemented early in the dev-elopment of the MECL III FLOGIC System is shown in Fig. 3. This Figure, in addition to showing MECL III FLOGIC in use, demonstrates the com-patibility of MECL III FLOGIC with the earlier FLOGIC work by this group (op.cit.) utilizing MECL II I.C. 's. When sc configured, the system speed is limited by the slower MECL II compon-ents and commensurate liberties can be taken with match·i ng the stri p-1 i ne impedanc~ from the MECL III FLOGIC cards. The modularity of the system is emphasized in the figure by cross-hatching the sections of the diagram at FLOGIC card boundaries. In this experiment the input signals are re-ceived from discriminators which transmit stand-ard NIM fast signal levels . At the inputs , eight "A" Gamma counter signals are ANDED with the corresponding eight "B " Gamma counter signals. Three distinct logical operations are perfonned : 1) A; ·B; ---a single-shot output pulse is provided as shown at the top center for each r(Ai)·r( B;) coincidence "hit ". 2) (A;·B;) · (-A (i+l).B(i+l)) ---a coin-cidence "hit " on any two adjacent r-r counters is recognized, as shown in the upper-right of the figure . 3) l: (A . . B. )>l, l:(A.·B . )>2, l:(A .. B.) >3 ---1 1 1 1 1 1 three outputs provide the analog OR'd sums of A.·B. "hits", as shown in the right-hand 1 cutouts. Top and bottom views of this system bin are shown in Figures 4 and 5 respectively. Notice that only two-thirds of bin capacity is required to provide the logic for this experiment. Notice also t hat the hardware i s particularly ·well suited for providing specialized circuitry; cards can be easily bread boarded and installed in the card-edge connectors. Following this experiment, the interconnections can be removed, and the cards and chassis will then be availabl e for the next experiment . (New front and rear panels will have to be provided.) " .. AI ~I 4. I / -3-I ~ J "ANALOG OR'D SUMS" v Fig. 3. r-r Experiment, FLOBIC Circuits Diagram ~ - ii ... -~· 1ll ,; r-r Experiment, FLOGIC Bin, Top View Fig. 5. r-r Experiment, FLOGIC Bin, Bottom View 3.0 - NIM Standa rd MECL III Fast Logic Modules A series of 300 MHz Nuclear Instrumentation modules utili zing MECL III I.C. 's has been built that offers NIM standardized siqnal levels and hardware packaging conveniences-to the user. A circuits building block concept has been employed -4-in the design of these modules. Four functional circuits , Input Level Shifter, Pulse Standardizer, Retriggerable One -Shot, and Output Level Shifter are the structura l elements which are appropriately com-bined and supplemented with special function circuits to generate the various NIM fast logic modules. @ INPUT fPWIIIM+W . 7064.53 !Nl IN2 @® IN3 IN4 ~ OUT 1 <IKt) The performance specificat i ons for the MECL III Fast Logic Modules: repeti t ion rates to> 300 MHz ; output rise-time, < 0.9 nsec; output fall time, < 1.2 nsec; mi nimum coincidence overlap, 0. 7 nsec above threshold; and coincidence resolution edges for 1000:1 count rate, < 40 ps are in keeping with the capabi l ities of the-M ECL III !.C.'s. Additional spec ifications include: signals standardized to NIM levels, inputs protected aga inst short transients to +l OOV (d .c. to +3 .5V) and po~1er requirements satisfied ~Y the standard- NIM type IV (+6V, +12V) power supply. MECL III Fast Logic Mod ul es designed to date are displayed in Fig. 6. ~@ INPUT MON • ADJ. MON . THRESHOLD Fig. 6. MECL III Fast Logic Modules .,; . ) u . •' ) / -_.;· -.,, -5-3.1 - Circuit Building Blocks The details of the four basic circuits used as building blocks in t~e design of MECL III Fq~t Logic Modules are presented in an earlier report.\ ) The general characteristics of the circuit building blocks are: 3.1.1 - Input Level Shifter Active semi-conductor junctions provide level shift between the center of the NIM fast signal levels and the center of the unique MECL III signal levels associated with the -GV VEE used in these modules. Except under extreme overload conditions, when thes€ junctions turn off to protect the MECL III I.C. ' s, these active junctions pass 1 ns signals with negligible deterioration. 3.1.2- Pulse Standardizer A pulse stand-ardizer uses the regenerative characteristics of a MECL III flip-flop and the stability characteristic of coaxial cables to provide output pulses of precise shape; independent of input rise-time and input width. 3.1.3- Retriggerable One-Shot Output pulse widths over the range of 3 ns to 100 ns are achieved by the use of a wide-range act i ve current pump and a charging capacitor. The charging cycle is initiated by "dumping" the capacitor with a standardized input pulse to a clamped level; thus stability and re-triggerability are achieved. 3.1.4- Output Level Shifter NIM outputs are provided from the collector of a transistor current switch. Twice NIM standard currents are switched into two parallel outputs; allowing one either to drive two circuits or to clip the output signal with a shorted transmission line on one output. 3.2 - Recent Module Developments The Discriminator and the Majority Logic Unit shown in Fig. 6 have recently been developed to fill out the selection of MECL III Fast Logic Modules. The building block approach is evident in the block diagrams of these modules, Figures 7 and 8. Clearly from thes€ block diagrams, there is but one functional element in each that dis-tinguishes between the two devices. To show the actual circuits used as buildinq blocks, the schematic of the MECL III discriminator is presented as Fig. 9. In the S-2 (lower) portion of this schematic, the two 12" cables and flip-flop , M3, identify the Pulse Standardizer section. Current pump Ql5 and capacitor C35 identify the Retriggerable One-Shot section. Output Level Shifters are evidenced by the current switching output transistors. Details on the theory of operation of these circuits can be obtained from the original works {op.cit.). The dis-criminator input circuit is modified from the stand-ard building block circuit to provide the exceptional speed and the critical offset balance required in a 50 mV broadband discriminator. The Schmitt tunnel diode discriminator is, of course, unique to this module. Fig. 7. MECL III Fast Logic Discriminator Block Diagram Fig. 8. MECL III Fast Logic Majority Logic Block Diagram Figure 10 shows the standard Input Level Shifter building block circuit as the input to the MECL III Majority Logic Unit. The two input diodes and the base-emitter junction of the first transistor comprise the protection and active level shift components. A clever utilization of the MECL III output transistor as one-half of a current switch in the majority logic summing section (Mla and Q6, for example) is shown in this figure. Beyond QlO, the circuits are of the common building block variety. 3.3 - Input Circuit Component Selection Although it is the intent of this paper to present only the concepts of the utilization of MECL III for High Energy Physics Instrumentation, a particularly sig-nificant detail has come to light that should be mentioned for the benefit of those contemplating the use of the input level shifters in this or in similar applications. It has been found that the diodes used for input protection and level shift have I-V characteristics that vary from production batch to production batch: within any given batch they appear to be fairly consistent. Therefore the self-explanatory nomogram, Fig. 11, has been designed to aid in the proper selection of resis-tors which, with these diodes , establish input off-set and provide signal level shift. ··~o.v" ~; 82. RIO 10 /, ALL RIHST41f;J 56 D.rt -'tW $~ COMI"l>Sif"ldl>/ I.J,_.<ISr ()T"I"'WI'Sil .S1"ICJf'1e.O. 2. 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EMDSA RA·OOZ~O OR KfN~ 1<!·71 · ()/ , ·-----------------------@ "T"Rf'H"O J'/ /1.1(1H" l iH Z973S·I .330 ~.~.~ ... -/<IXZf73$-Z I Fig . 9 MECL III Fast Logic, Discriminator Schematic Diagram INH!J Yo .t SMA . ·, ~ ) ' • . J .) ) .:; -7-\..IN747A z.sv e ,..,A Fig. 10. MECL III Fast Logic, Majority Logic Input Section Schematic Diagram 1111: 10>110£ -AIIUTIO•S Ill I~'S .o.HD , ... ~~>7 otOO£ o~o,s vttH orrnuu 8ATCHU, 11 HU IHIIJI(CUSAIIT TO ~[l(CJ Vloi.UU TOll Rl AID l2 TO COIY'USUt Hlll. TM£U VMIA11011S, THIS~IOAJ.MAI.LOW$011(10USIL1 S[l((lll.l oU1D U TO IU.l(ll TIK DIOIIU. SUI((OI OOUWillfiiiAGIYllltATtll l{ICI TO I[ Qlllf( CCIIISUllllt, Tilt lVEil.Wil 1:111.01 0# • H~ OIOCIU Mill It uno lOOUliUUta: C(Jtot)ll YM,UU 0# ... . .. ..•• I.U 1.1 11 ... .•. "' ft2 touu, I, Mt:ASUIU TII(YCI.l"'£01l0,a(.11.0U UC/10100( AT 5-lrolllllll(~V( TIU.C{.I.OII.VOlTMt:Tlll. I . l.UASTU I ~T lOG£ SUCH l HU 111( £0(0(CIIOUUTll( HUSIM£0 OIU)1'1011 Til[ I""S 011 IU KAU AICI1H(!WASUIH00110'TOJITH( lltl,lolo7 OHTH£0TH£11 $UU. J , lH£ ZOIIU I IMU WHICH 111£ STUtliHT £01il'•U5UOM liiiUIWIK£0 111 &.IIOU IICI IUH TH£ Vo\1.\IU TO I( IN4447 Vc &I liMA • •u .;., tMu..r .. l/oll !I lh. ---- IW1'1 14X3021 O-IA Fig. 11. MECL III Fast Logic, Input Section-Resistor Selection Nomogram REFERENCES 1) F. A. Kirsten and D. A. Mack, System of Fast Integrated Circuit Logic for Physics Instru-mentation, International Symposium on Nuclear Electronics, Versailles, France, Sept. 1968, pp 55-1 to 55-12. 2) AEC Committee on Nuclear Instrument Modules , Standard Nuclear Instrument Modules, TID 3) 20893 (Rev. 3), U.S . Atomic Energy Commission, December 1969. R. F. Althaus and L. W. Nagel, NIM Fast Logic Utilizing MECL III Integrated Circuits , IEEE Trans . on ~uclear Science, NS-19, No. 1, Feb . 1972, pp 520-525. 1 j r------------------LEGALNOTICE---------------------. This report was prepared as an account of work sponsored by the United States Government. Neither the United States nor the United States Atomic Energy Commission, nor any of their employees, nor any of their contractors, subcontractors, or their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness or usefulness of any information, apparatus, product or process disclosed, or represents that its use would not infringe privately owned rights. ... "' ·-. TECHNICAL INFORMATION DIVISION LAWRENCE BERKELEY LABORATORY UNIVERSITY OF CALIFORNIA BERKELEY, CALIFORNIA 94720 -

English

ON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATION

Althaus, R. F.

Lee, K. L.

Kirsten, F. A.

Wagner, L. J.

UNT Digital Library

ON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATION* R. F. AUhaus, K. L. Lee, F. A. Kirsten and L. J. Wagner Lawrence Fierkeley Laboratory University of California Berkeley, CA 94720 1. - Summary Commercially available high speed digital integrated circuits (I.C.'s) now have performance characteristics and economy that make them attractive as central logical elements around which state-of-the-art instruments for High Energy Physics can be developed. In work reported five years ago^ 1' commercial I.C.'s were shown to offer advantages of economy and packaging density, which were valued in some large system arrays, but their performance was below that of the 200 MHz commercially available counting equipment. No longer must speed, or re­solution, be compromised for these advantages. Cir­cuits now configured around the Motorola** MECL III line of integrated circuits provide 300 MHz speed, 1.2 ns maximum rise- or fall-time, coincidence re­cognition for 1 ns overlap, and Inherent coincidence time resolution edges of less than 40 ps (1000:1 count rate). Two modular packaging schemes using MECL III I.C.'s have been developed at the Lawrence Berkeley Laboratory. The first to be described, called the FLOGIC System, achieves high packaging density by means of logic cards that are interconnected in a custom design utiique to each experiment. The FLOGIC System is most suitably used where many channels of instrumentation are required and the configuration of these channels, once established, is not subject to frequent unprescribed change. The second scheme uses the NIM Standard(2) hardware. This scheme offers the convenience and versatility of standardized hardware and signal levels. 2. - THE FLOGIC System The FLOGIC System is modular at the printed circuit card level. Small (55mm X 114mm) printed circuit cards containing I.C. gates and registers are interconnected to perform the logical functions desired for a specific application. Achieving this modularity in a manner consistent with the performance characteristics of the MECL I.C.'s and with economi­cally practical hardware were the dichotomous ob­jectives of this system. Subminiature coaxial connec­tors, as a natural first consideration for inter­connection, match the performance characteristics, but are prohibitively expensive and leave the distri­bution of d.c. power as a separate consideration. *Work done under the auspices of USAEC "Motorola Semiconductor Products, Inc. Phoenix, Arizona, U.S.A. - N O T I C E -This report w u prepued is an account of work sponsored by the United States Government. Neither the United 5tates nor the United States Atomic Energy Commission, nor any of their employees, nor any of their contractors, subcontractors, or their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, com. pletenes* or usefulness of any information, apparatus, product or process disclosed, or represents that its use would not infringe privately owned rights. Unique utilization of standard commercial com­ponent parts provides performance at an attractive cost. Interconnection is accomplished by means of DIAD connectors, an adaptation of the Termi-twist/ Termi-point printed circuit card-edge connector series manufactured by AMP.* The overall system is packaged in bins available from Data-Tech.** Power can be provided by any modular floating 5.2V power supply; a floating supply is used to shift the usual MECL III logic signal levels of -0.8V and -1.6V to approximately 0V and -0.8V, compatible with the NIM standard. 2.1 - MECL III FLOGIC cards Figure 1 shows a MECL III FLOGIC card in which you can see the strip-line input and output fast sig­nal lines required by the nominally 1 ns signal tran­sition speed of the I.C.'s. Output signal strip-lines have a characteristic impedance (Z 0) of 50ft; they are the four wide strip-lines on the card. Pulldown resis­tors of 180fi for each of these outputs are located adja­cent to the I.C. Inputs, the eight narrow strip-lines, are run at lOOn Z 0 to conserve on printed surface area; these lines are shunted with lOOfi resistors at the card-edge to terminate the 50n input coax, and are terminated at the I.C. with a lOOfi strip-line match. As a shadow, you can see the plane conductor surface on the reverse side of the card that serves as refer­ence for the strip-lines. The lower portion of this plane surface is at common potential, but the upper portion is at -4.4V, V ee. as required for the stud connection on the I.C. A row of capacitors provides a.c. signal continuity across these two plane sur­faces. The remaining trace is the +0.8V, V c c conductor. 2.2 - DIAD Connectors Figure 1 also shows the interconnecting hardware. Inexpensive Termi-point clips are solder-mounted onto the small printed pads shown at the top of the figure to produce DIAD connectors as shown in front and rear views in Fig. 2. The pads have a plane surface on one side, to which the coax braid is referenced. On the other side, to which the Termi-point clips are soldered, a strip-line is printed as the signal con­ductor. A capacitive mismatch at the clip end of the DIAD, caused by the very presence of the clips, is used to advantage. It is trimmed, by voiding a section of the rear plane surface, to just combine with a small inductive lump in the rearward pin extension of the Termi-twist connector socket contact and a capacitive lump at the forward extension of the contact (due to dielectic effects of the connector block) to provide a C-L-C lumped constant section of 50fi line with transit *AMP Incorporated, Harrisburg, Pennsylvania, U.S.A. **Data Technology, Corp., Palo Alto, California, U.S.A. U ! o ! :-.J,_-'J . 5 UNLIMITED ^ ! » I Fig. 1. MECL III Flogic System Components Fig. 2. DIAD Connector for MECL III FLOGIC System time short enough to be inconsequential to the 1.2 ns rise-time signal out of the MECL III I.C.'s, when driving a 50n load. Tests show this compen­sated DIAD connector to pass a 200 ns 10-90% rise-time signal with undetectable deterioration of 10-90% rise-time, whereas an uncompensated version, with the same Termi-point clip, deteriorates the 200 ps 10-90% rise-time to 700 ps. 2.3 - A FLOGIC Instrumented Experiment An experiment implemented early in the dev­elopment of the MECL III FLOGIC System is shown in Fig. 3. This Figure, in addition to showing MECL III FLOGIC in use, demonstrates the com­patibility of MECL III FLOGIC with the earlier FLOGIC work by this group (op.cit.) utilizing MECL II I.C.'s. When so configured, the system speed is limited by the slower MECL II compon­ents and commensurate liberties can be taken with matching the strip-line impedance from the MECL III FLOGIC cards. The modularity of the system is emphasized in the figure by cross-hatching the sections of the diagram at FLOGIC card boundaries. In this experiment the input signals are re­ceived from discriminators which transmit stand­ard NIM fast signal levels. At the inputs, eight "A" Gamma counter signals are ANDED with the corresponding eight "B" Gamma counter signals. Three distinct logical operations are performed: 1) A. -p^ — a single-shot output pulse is provided as shown at the top center for each r(A-)T(B.) coincidence "hit". 2) C y B i M A ^ - B ^ ) ) - a coin-cidence "hit" on any two adjacent r-r counters is recognized, as shown in the upper-right of the figure. 3) S(A..B1)>1, r(A..B.)>2, E( A 1 . B . ) > 3 — three outputs provide the analog OR'd sums of A.-B. "hits", as shown in the right-hand outputs. Top and bottom views of this system bin are shown in Figures 4 and 5 respectively. Notice that only two-thirds of bin capacity is required to provide the logic for this experiment. Notice also that the hardware is particularly well suited for providing specialized circuitry; cards can be easily bread boarded and installed in the card-edge connectors. Following this experiment, the interconnections can be removed, and the cards and chassis will then be available for the next experiment. (New front and rear panels will have to be provided.) . „ * * * • .H*4n.... mmm-w ~~w? 'tSZr^fpt&Z! H M ANALOG Cft'O SUMS" JMMxmur */»rt; &t*t*f &*/#+ Sjtftt, f»* Mtur ft JAM* iktftr* • ,i~- — Fig. 3. r-r Experiment, FLOGIC Circuits Diagram V 4 0 %'"' g. 4. r-r Experiment, FLOGIC Bin, Top View Fig. 5. r-r Experiment, FLOGIC Bin, Bottom View -4-3.0 - NIM Standard MECL III Fast Logic Modules A series of 300 MHz Nuclear Instrumentation modules utilizing MECL III I.C.'s has been built that offers NIM standardized signal levels and hardware packaging conveniences to the user. A circuits building block concept has been employed in the design of these modules. Four functional circuits, Input Level Shifter, Pulse Standardizes Retriggerable Ora-Shot, and Output Level Shifter are the structural lements which are appropriately com­bined and sup:.-lamented with special function circuits to generate the various NIM fast logic modules. The performance specifications for the MECL III Fast Logic Modules: repetition rates to > 300 MHz: output rise-time, < 0.9 nsec; output fall time, <_ 1.2 nsec; minimum coincidence overlap, 0.7 nsec above threshold; and coincidence resolution edges for 1000:1 count rate, ^ 4 0 ps are in keeping with the capabilities of the MECL III I.C.'s. Additional specifications include: signals standardized to NIM levels, inputs protected against short transients to +100V (d.c. to +3.5V) and power requirements satisfied by the standard NIM type IV (+6V, +12V) power supply. MECL III Fast Logic Modules designed to date are displayed in Fig. 6. Fig. 6. MECL III Fast Logic Modules -5-3.1 - Circuit Building Blocks The details of the four basic circuits used as building blocks in the design of MECL III Fast Logic Modules are presented in an earlier report.'3' The general characteristics of the circuit building blocks are: 3.1.1 - Input Level Shifter Active semi­conductor junctions provide level shift between the center of the NIM fast signal levels and the center of the unique MECL III signal levels associated with the -6V V E £ used in these modules. Except under extreme overload conditions, when these junctions turn off to protect the MECL III I.C.'s, these active junctions pass 1 ns signals with negligible deterioration. 3.1.2 - Pulse Standardizer A pulse stand­ardizer uses the regenerative characteristics of a MECL III flip-flop and the stability characteristic of coaxial cables to provide output pulses of precise shape; Independent of input rise-time and input width. 3.1.3 - Retrlgqerable One-Shot Output pulse widths over the range of 3 ns to 100 ns are achieved by the use of a wide-range active current pump and a charging capacitor. The charging cycle is Initiated by "dumping" the capacitor with a standardized input pulse to a clamped level; thus stability and re-triggerability are achieved. 3.1.4 - Output Level Shifter NIM outputs are provided from the collector of a transistor current switch. Twice NIM standard currents are switched into two parallel outputs; allowing one either to drive two circuits or to clip the output signal with a shorted transmission line on one output. 3.2 - Recent Module Developments The Discriminator and the Majority Logic Unit shown in Fig. 6 have recently been developed to fill out the selection of MECL III Fast Logic Modules. The building block approach is evident 1n the block diagrams of these modules. Figures 7 and 8. Clearly from these block diagrams, there is but one functional element in each that dis­tinguishes between the two devices. To show the actual circuits used as bulldinq blocks, the schematic of the MECL III discriminator is presented as Fig. 9. In the S-2 (lower) portion of this schematic, the two 12" cables and flip-flop, M3, identify the Pulse Standardizer section. Current pump Q15 and capacitor C35 identify the Retriggerable One-Shot section. Output Level Shifters are evidenced by the current switching output transistors. Details on the theory of operation of these circuits can be obtained from the original works (op.cit.). The dis­criminator input circuit is modified from the stand­ard building block circuit to provide the exceptional speed and the critical offset balance required in a 50 mV broadband discriminator. The Schmitt tunnel diode discriminator is, of course, unique to this module. r-E™Hl[g £3—I """"•!— Kg Kg Fig. 7. MECL I I I Fast Logic Discriminator Block Diagram r—il" 3 —*—1/K/rwrl—f-T3 Fig. 8. MECL III Fast Logic Majority Logic Block Diagram Figure 10 shows the standard Input Level Shifter building block circuit as the input tc the MECL III Majority Logic Unit. The two input diodes and the base-emitter junction of the first transistor comprise the protection and active level shift components. A clever utilization of the MECL III output transistor as one-half of a current switch 1n the majority logic summing section (Mia and Q6, for example) is shown in this figure. Beyond Q10, the circuits are of the common building block variety. 3.3 - Input Circuit Component Selection Although it is the intent of this paper to present only the concepts of the utilization of MECL III for High Energy Physics Instrumentation, a particularly sig­nificant detail has come to light that should be mentioned for the benefit of those contemplating the use of the input level shifters in this or in similar applications, it has been found that the diodes used for input protection and level shift have I-V characteristics that vary from production batch to production batch: within any given batch they appear to be fairly consistent. Therefore the self-explanatory nomogram. Fig. 11, has been designed to aid in the proper selection of resis­tors which, with these diodes, establish input off­set and provide signal level shift. -6-MOTESt t. An. CAPACITIES inf cetAtr.it ffc.r. CKOS Tree a^c's o-"^ <E SF/.'.' -P. Z. fit., D.~D£S )N44-t? (JWl.fi;.'. Or*£.Zs.'?£ SP£C!Ft£D. 3. All. Rffi'cA'S ht-VJ S% CCMPosirton cJUsi o-»iK<.Jire. sreZ'SIID. tji*. .75 ir f£St:r-K . r*i ro /•>:•* l f CF .HZ ">*. "«« ,,| f«. „.f 4" <^" «a | f4*Z9 73f rT" | Mo,, F.» it 3. An. C'OPta IK++4T UHLItl OT*l**it* ! » « » " « . M 4. L I 4 12 AH 3 TVXMt **0 iMAMtLtO COr*l* Witt OM ri**<rt COM S. Mrefot*** : mi, f*, »*, *** *** Md**Bi 1 <w+ 'J w / * « u V *,* i i i* Art &»», l i. All. CMMCiDJ ( 1 M » iw-eeiw oa *>•»• xiJi-oi t w i n o r « » « J ( j .'. COAtlAl CAB*.** If ACIttA/ti. 3 l k •zgy L §-r& «-*# :=Cr •=2cr Si a 'W, "tl'g-r—i * j r^ii-11 i 1 1 — " " " ^ M T T 6 ' r 1 "* jEtebl rn 1.1 1"! 1 tfflll IWHK nun = =̂  = 7 = J _ f f4X£173&2 , Fig. 9 MECL III Fast Logic, Discriminator Schematic Diagram -7-F1g. 10. MECL III Fast Logic, Majority Logic Input Section Schematic Diagram M TO 101 MaiUIOM 1 IDTti U6 IVAk? tCCt H 0 * l HltH i n u i K i incnt t I I Hit M i l MC » M T IB SClfCI n i K l f « m *» M 10 COMklATt rp» INIU M l Hi i o n . THII Ml W I M U W I M 10 IUTLT I I L U I 1 I K I I I t MICH ft • ! < • » • I I 1 U I • 1 1 HIHIM • • m i f t o i T I N 10 M OVIII COM I t ! «. M IVIUCt MO* Of I F N * Mil W H mi re H K W I I <0>MM Mtm*o» >i * •> • I . Q%1 wo. m twi CIKWI 1. K I W I THI rCLTUI .» « . M l IXH I1CCI »T M « H * ( » « !Mcn«wm«ru 1 . L « 1 ITUICHI <0U U W t M l THI IKC U O I I t t TOT HUlMtO HOP rot THI I W S 0 • I I I M i l l UO TM MUIKIX Wa * rm rw '»">> <* ™« < ™ " K J U . 1. IM Hum IMU WICH T« 1TMI0HT i K t M H I I W i n n n u r f i i f H t ^ U > « I » T ( THI " " " TO M HWOJW norcwaww 14X3021D-1A •m F1P, 11. MECL III Fast Logic, Input Section Resistor Selection Nomogram REFERENCES 1) F. A. Kirsten and C. A. Mack, System of Fast Integrated Circuit Logic for Physics Instru-I.Î  JLion, International Symposium on Nuclear Electronics, Versailles, France, Sept. 1968, pp 55-1 to 55-12. 2) AEC Committee on Nuclear Instrument Modules, Standard Nuclear Instrument Modules, TIC 20893 (Rev. 3), U.S. Atomic Energy Commission, December 1969. 3) R. F. Althaus and L. W. Nagel, M M Fast Logic Utilizing MECL III Integrated Circuits, IEEE Trans, on Nuclear Science, HS-19, No. 1, Feb. 1972, pp 520-525. 

Using high speed digital integrated circuits for nuclear instrumentation

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ON USING HIGH SPEED DIGITAL INTEGRATED CIRCUITS FOR NUCLEAR INSTRUMENTATION

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