This communication presents the evidence of a degradation effect causing important
reductions in the delay of a CMOS inverter when consecutive input transition are close
in time. Complete understanding of the effect is demonstrated, providing a quantifying
model. Fully characterization as a function of design variables and external conditions
is carried out, making the model suitable for using in library characterization as well as
simulation at a transistor level. Comparison with HSPICE level 6 simulations shows
satisfactory accuracy for timing evaluation.Comisión Interministerial de Ciencia y Tecnología TIC 95-009