Testing of an electronic chip is an important step in the design process, as it can detect faults and ensure reliability. Design for Test (DFT) methods are used to modify existing designs to enable their testing by Automatic Test Pattern Generators. This thesis focuses on developing testing techniques for design automation of NULL Conventional Logic (NCL) circuits and for detection of capacitive crosstalk effects in Field Programmable Gate Arrays (FPGAs).
A novel technique is developed for testing asynchronous NCL designs aimed at good fault coverage with acceptable gate overhead. The technique focuses on testing stuck-at-faults in the internal feedback paths of NCL primitive gates and global feedback paths of the design. Controllability of the feedback paths and observability of the fault sites are enhanced to improve the testability of the design. Observability of the fault sites is improved based on Sandia Controllability And Observability Program (SCOAP) values, in order to reduce the gate overhead. This work also includes the automation of the testing process.
A framework is proposed on the detection of capacitive crosstalk noise in FPGAs focusing on faults due to manufacture defects and process variations a framework. The approach is based on detecting crosstalk effects such as glitches and delayed transitions among the interconnect structure in FPGAs based on the Maximum Aggressor Fault model. Novel test architectures for Test Pattern Generator and Analyzer are presented. Enhancement in the existing cost function is also proposed to avoid the routing of interconnects affected by crosstalk noise in FPGAs --Abstract, page iii
